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參數(shù)資料
| 型號： | AM79C901AVC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP80 |
| 封裝： | PLASTIC, MO-136BAM, TQFP-80 |
| 文件頁數(shù)： | 26/90頁 |
| 文件大?。?/td> | 714K |
| 代理商： | AM79C901AVC |
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26
Am79C901A
P R E L I M I N A R Y
Figure 8.
RXPKT - CLS Asserted
Table 2.
GPSI Timing
Note:
During the AID interval, TXCLK and RXCLK
stop for up to 140
μ
s.
Serial Peripheral Interface (SPI-Slave)
Mode
When MII/GPSI is set to 0, the device is in
“
SPI
”
mode.
The device acts as an SPI slave peripheral in this mode
of operation. Commands are issued to the device by
asserting the CS signal (active low), shifting in an 4-bit
opcode, followed by an 10-bit register address and
2 bits of end delimiter. If the operation is a write, the
data bits are written into the desired register. If the op-
eration is a read, then these data bits are ignored. The
SDO pin will shift out 16 data bits representing the con-
tents of the register referenced by the address field for
read operations. All commands must be initiated with a
high-to-low transition on the CS pin. Only one com-
mand can be sent in one CS cycle.
For assistance in debugging access to the SPI inter-
face, an error code is driven onto the SDO. If there is
less than 32 bits of SCLK during the time that CS is as-
serted, the error code field of SDO on the next com-
mand will indicate AAAA. When there is an incorrect
opcode in the command on SDI AAAA will be immedi-
ately driven out on SDO until CS deasserts. If there are
more than 32 clock cycles while CS is low, the first 32
are assumed to contain the data, and the additional
clock bits and associated data are ignored. In this case,
the SDO might generate AAAA under the additional
clock bits. See Figure 9.
Figure 9.
Operation of the SPI Interface
TXCLK
TXEN
TXDAT
RXCLK
RXCRS
RXDAT
CLS
22304B-10
Note:
CLS may be asserted up to 120
μ
s after RXCRS has been asserted. Once CLS has been asserted,
TXCLK and RXCLK run until 96 cycles after CLS and RXCRS are cleared. It can take a maximum of approxi-
mately 60
μ
s for RXCRS to clear.
Condition
CLK Period
CLK Frequency
Idle (excluding
IPG time)
583.3 ns
1.7 MHz
Preamble (first 64
bits of TX MAC
frame)
233.3 ns
4.3 MHz
Data (throughout
the data phase)
100 ns -
10
μ
s
1.0 MHz avg.
IPG (96 bit times
following CRS
↓)
233.3 ns
4.3 MHz
SCLK
CS
SDI
SDO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
32
Op Codes
Address
Data In
Data Out
Error Code
22304B-11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C901AVCT | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C901AVI | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C901AVIT | HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C90 | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C901AVC/w | 制造商:Advanced Micro Devices 功能描述:79C901AVC/W |
| AM79C901AVC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C901AVC\W | 制造商:Advanced Micro Devices 功能描述:PHY 1-CH 1Mbps/10Mbps 80-Pin TQFP |
| AM79C901AVCT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
| AM79C901AVI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:HomePHY Single-Chip 1/10 Mbps Home Networking PHY |
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