參數(shù)資料
型號(hào)： AM79C901AVC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 網(wǎng)絡(luò)接口
英文描述： HomePHY Single-Chip 1/10 Mbps Home Networking PHY
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP80
封裝： PLASTIC, MO-136BAM, TQFP-80
文件頁(yè)數(shù)： 28/90頁(yè)
文件大?。?/td> 714K
代理商： AM79C901AVC
28
Am79C901A
P R E L I M I N A R Y
Figure 13.
Normal Operation
MII-Compatible Interface for HomePNA
PHY
The control and data signals that are utilized in the MII-
compatible interface of the 1 Mbps HomePNA PHY
function in an manner that is identical to that as defined
in the 802.3u specification. The signals RX_CLK and
TX_CLK function in a slightly different manner in that
they operate at a reduced data rate and that these
clock signals do not run at a constant rate due to the
RLL25
encoding scheme. See Table 4.
Table 4.
MII-Compatible Timing
Note:
During the AID interval, TX_CLK and RX_CLK
stop for up to 140
μ
s.
Figure 14 and Figure 15 represent the signal relation-
ships when the MII-compatible data interface is utilized.
The signals TX_CLK and RX_CLK will toggle at a rate
of approximately 428 kHz during idle time. When the
TX_EN signal is asserted to indicate the beginning of a
transmission, the clock rate will enter the preamble
phase. Once the SFD has been detected and the
HomePNA PHY has begun the transmission of the
HomePNA header, the clock enters the data phase.
When the TX_EN signal is deasserted to indicate the
ending of a transmission, TX_CLK is halted until the
RXDATA path detects the end of the packet. At this
time, the clock rate is increased to the IPG data rate for
96 bit times and then returns to the Idle state.
MII-Compliant Interface for 10BASE-T PHY
The MII interface is fully IEEE 802.3u-compliant when
the 10BASE-T PHY is selected. The management in-
terface specified in Clause 22 of the IEEE 802.3u stan-
dard provides for a simple two wire, serial interface to
connect a management entity and a managed PHY for
the purpose of controlling the PHY and gathering sta-
tus information. The two lines are Management Data
Input/Output (MDIO) and Management Data Clock
(MDC). A station management entity, which is attached
to multiple PHY entities, must have prior knowledge of
the appropriate PHY address for each PHY entity.
The management interface physically transports man-
agement information across the MII. The information
is encapsulated in a frame format as specified in
Clause 22 of the IEEE 802.3u standard and is shown
in Table 5.
Table 5.
MII Control Frame Format
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
32
Op Codes
Address
Data In
Data Out
Error Code = 0
SCLK
CS
SDI
SDO
22304B-15
Condition
CLK Period
CLK
Frequency
Idle (excluding IPG
time)
2333.34 ns
428.6 kHz
Preamble (first 64 bits
of TX MAC frame)
933.33 ns
1.07 MHz
Data (throughout the
data phase)
400 ns - 40
μ
s
250 kHz avg.
IPG (96 bit times
following CRS
↓
)
933.33 ns
1.07 MHz
PRE
ST
OP
PHYADD
REGADD
TA
DATA
IDLE
READ
1...1
01
10
AAAAA
RRRRR
Z0
D15
………
D0
Z
WRITE
1...1
01
01
AAAAA
RRRRR
10
D15
………
D0
Z
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參數(shù)描述
AM79C901AVC/w 制造商:Advanced Micro Devices 功能描述:79C901AVC/W
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AM79C901AVI 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:HomePHY Single-Chip 1/10 Mbps Home Networking PHY
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