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參數(shù)資料
| 型號(hào)： | AM79C90PC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| 中文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 26/62頁 |
| 文件大?。?/td> | 437K |
| 代理商： | AM79C90PC |
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AMD
P R E L I M I N A R Y
26
Am79C90
The Broadcast address, which consists of all ones is a
special multicast address. Packets addressed to the
broadcast address must be received by all nodes. Since
broadcast packets are usually more common than other
multicast packets, the broadcast address should be the
first address in the multicast address list.
The Broadcast address does not go through the Logical
Address Filter and is always enabled. If the Logical Ad-
dress Filter is loaded with all zeroes, all incoming logical
addresses except broadcast will be rejected. The multi-
cast addressing in external loopback is operational only
when DTCR in the mode register is set to 1.
Destination
Address
47
1 0
CRC
Gen
32-Bit Resultant CRC
31
26
0
Logical Address
Filter
63
0
“1”
Enable
64
MUX
Select
Match*
6
*Match - 1, the packet is accepted
Match - 0, the packet is rejected
17881B-22
Figure 7. Logical Address Filter Operation
Receive Descriptor Ring Pointer
31
2 0
17881B-23
2928 24 23
3
RES
RLEN
000 ‘(Quadword
Boundary)’
RDRA (23:03)
Bit
Name
Description
31:29
RLEN
RECEIVE RING LENGTH is the
number of entries in the receive ring
expressed as a power of two.
RLEN
Number of Entries
0
1
2
3
4
5
6
7
RESERVED. Read as zeroes. Write
as zeroes.
RECEIVE DESCRIPTOR RING AD-
DRESS is the base address (lowest
address) of the Receive Descriptor
Ring.
MUST BE ZEROES. These bits are
RDRA (02:00) and must be zeroes
because the Receive Ring is aligned
on a quadword boundary.
1
2
4
8
16
32
64
128
28:24
RES
23:03
RDRA
02:00
Transmit Descriptor Ring Pointer
31
2 0
17881B-24
2928 24 23
3
RES
TLEN
000 ‘(Quadword
Boundary)’
TDRA (23:03)
31:29
TLEN
TRANSMIT RING LENGTH is the
number of entries in the Transmit
Ring expressed as a power of two.
TLEN
Number of Entries
0
1
2
3
4
5
6
7
RESERVED. Read as zeroes. Write
as zeroes.
TRANSMIT DESCRIPTOR RING
ADDRESS is the base address (low-
est address) of the Transmit De-
scriptor Ring.
MUST BE ZEROES. These bits are
TDRA (02:00) and must be zeroes
because the Transmit Ring is
aligned on a quadword boundary.
1
2
4
8
16
32
64
128
28:24
RES
23:03
TDRA
02:00
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C90PCTR | CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C930 | PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
| AM79C930VCW | PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
| AM79C940VCW | Media Access Controller for Ethernet (MACE) |
| AM79C940 | Media Access Controller for Ethernet (MACE) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C90PCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Node Controller |
| AM79C90PCTR | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:CMOS Local Area Network Controller for Ethernet (C-LANCE) |
| AM79C90WW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C930 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-Mobile Single-Chip Wireless LAN Media Access Controller |
| AM79C930EVAL-HW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Am79C930EVAL-HW - PCnet-Mobile Evaluation Kit |
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