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參數(shù)資料
| 型號(hào)： | AM79C970AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 206/219頁 |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970AVCW |
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AMD
D-2
Am79C970A
Outline of the LAPP Flow
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the PCnet-PCI II controller.
Note
: The labels in the following text are used as refer-
ences in the timeline diagram that follows.
SETUP:
The driver should set up descriptors in groups of 3, with
the OWN and STP bits of each set of three descriptors to
read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5;
the software should set this bit; When set, the LAPPEN
bit directs the PCnet-PCI II controller to generate an
INTERRUPT when STP has been written to a receive
descriptor by the PCnet-PCI II controller.
FLOW:
The PCnet-PCI II controller polls the current receive de-
scriptor at some point in time before a message arrives.
The PCnet-PCI II controller determines that this receive
buffer is OWNed by the PCnet-PCI II controller and it
stores the descriptor information to be used when a
message does arrive.
N0:
Frame preamble appears on the wire, followed by
SFD and destination address.
N1: The 64th byte of frame data arrives from the wire.
This causes the PCnet-PCI II controller to begin
frame data DMA operations to the first buffer.
C0: When the 64th byte of the message arrives, the
PCnet-PCI II controller performs a lookahead
operation to the next receive descriptor. This
descriptor
should
PCnet-PCI II controller.
C1: The PCnet-PCI II controller intermittently requests
the bus to transfer frame data to the first buffer as it
arrives on the wire.
S1: The driver remains idle.
C2: When the PCnet-PCI II controller has completely
filled the first buffer, it writes status to the
first descriptor.
C3: When the first descriptor for the frame has been
written, changing ownership from the PCnet-PCI
II controller to the CPU, the PCnet-PCI II controller
will generate an SRP INTERRUPT. (This interrupt
appears as a RINT interrupt in CSR0).
S1: The SRP INTERRUPT causes the CPU to switch
tasks to allow the PCnet-PCI II controllers driver
to run.
C4: During the CPU interrupt-generated task switch-
ing, the PCnet-PCI II controller is performing a
lookahead operation to the third descriptor. At this
point in time, the third descriptor is owned by
the CPU.
be
owned
by
the
Note
: Even though the third buffer s not owned by
the PCnet-PCI II controller, existing AMD Ethernet
controllers will continue to perform data DMA into
the buffer space that the controller already owns
(i.e., buffer number 2). The controller does not
know if buffer space in buffer number 2 will be suf-
ficient or not, for this frame, but t has no way to tell
except by trying to move the entire message into
that space. Only when the message does not fit
will it signal a buffer error condition – there is no
need to panic at the point that it discovers that it
does not yet own descriptor number 3.
S2: The first task of the drivers interrupt service rou-
tine is to collect the header information from the
PCnet-PCI II controllers first buffer and pass it to
the application.
S3: The application will return an application buffer
pointer to the driver. The driver will add an offset to
the application data buffer pointer, since the
PCnet-PCI II controller will be placing the first por-
tion of the message into the first and second buff-
ers. (The modified application data buffer pointer
will only be directly used by the PCnet-PCI II con-
troller when it reaches the third buffer.) The driver
will place the modified data buffer pointer into
the final descriptor of the group (#3) and will
grant ownership of this descriptor to the
PCnet-PCI II controller.
C5: Interleaved with S2, S3 and S4 driver activity, the
PCnet-PCI II controller will write frame data to
buffer number 2.
S4: The driver will next proceed to copy the contents
of the PCnet-PCI II controllers first buffer to the be-
ginning of the application space. This copy will be
to the exact (unmodified) buffer pointer that was
passed by the application.
S5: After copying all of the data from the first buffer
into the beginning of the application data buffer,
the driver will begin to poll the ownership bit of the
second descriptor. The driver is waiting for the
PCnet-PCI II controller to finish filling the
second buffer.
C6: At this point, knowing that it had not previously
owned the third descriptor, and knowing that the
current message has not ended (there is more
data in the FIFO), the PCnet-PCI II controller will
make a last ditch lookahead to the final (third) de-
scriptor. This time, the ownership will be TRUE
(i.e. the descriptor belongs to the controller), be-
cause the driver wrote the application pointer into
this descriptor and then changed the ownership to
give the descriptor to the PCnet-PCI II controller
back at S3. Note that if steps S1, S2 and S3 have
not completed at this time, a BUFF error will result.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971 | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AVI\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AVI\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AVIW | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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