Publication#
20550
Issue Date:
May 2000
Rev:
E
Amendment: /
0
Am79C971
PCnet-
FAST
Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
DISTINCTIVE CHARACTERISTICS
I
Single-chip Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) local
bus
—
32-bit glueless PCI host interface
—
Supports PCI clock frequency from DC to
33 MHz independent of network clock
—
Supports network operation with PCI clock
from 15 MHz to 33 MHz
—
High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
—
PCI specification revision 2.1 compliant
—
Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
—
Supports both PCI 5.0-V and 3.3-V signaling
environments
—
Plug and Play compatible
—
Supports an unlimited PCI burst length
—
Big endian and little endian byte alignments
supported
I
Integrated 10BASE-T and 10BASE-2/5 (AUI)
Physical Layer Interface
—
Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3
and Blue Book Ethernet-compliant solution
—
Automatic Twisted-Pair receive polarity
detection and correction
—
Internal 10BASE-T transceiver with Smart
Squelch to Twisted-Pair medium
—
IEEE 802.3-compliant auto-negotiable
10BASE-T interface
I
Supports General Purpose Serial Interface
(GPSI)
I
Media Independent Interface (MII) for
connecting external 10- or 100-Megabit per
second (Mbps) transceivers
—
IEEE 802.3-compliant MII
—
Intelligent Auto-Poll
external PHY status
monitor and interrupt
—
Includes intelligent on-chip Network Port
Manager that provides auto-port selection
between MII, on-chip 10BASE-T port, and AUI
without software support
—
Supports both auto-negotiable and non
auto-negotiable external PHYs
—
Supports 10BASE-T, 100BASE-TX/FX,
100BASE-T4, and 100BASE-T2 IEEE 802.3-
compliant MII PHYs at full- or half-duplex
I
Internal/external loopback capabilities on all
ports
I
Supports patented External Address Detection
Interface (EADI)
—
Receive frame tagging support for inter-
networking applications
I
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards
I
Full-duplex operation supported in AUI,
10BASE-T, MII, and GPSI ports with
independent Transmit (TX) and Receive (RX)
channels
I
Flexible buffer architecture
—
Large independent internal TX and RX FIFOs
—
SRAM-based FIFO buffer extension
supporting up to 128 kilobytes (Kbytes)
—
1/2 Gigabit per second (Gbps) internal data
bandwidth
—
Programmable FIFO watermarks for both TX
and RX operations
—
RX frame queuing for high latency PCI bus
host operation
—
Programmable allocation of buffer space
between RX and TX queues
I
EEPROM interface supports jumperless design
and provides through-chip programming
—
Supports full programmability of half-/full-
duplex operation for external 100 Mbps PHYs
through EEPROM mapping
I
Extensive LED status support