參數(shù)資料
型號(hào)： AM79C972BKCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 106/130頁(yè)
文件大?。?/td> 1580K
代理商： AM79C972BKCW
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106
Am79C972
Am79C972 control registers. A
read access will yield undefined
values.
Read/Write accessible always.
RAP is cleared by H_RESET or
S_RESET and is unaffected by
setting the STOP bit.
Control and Status Registers
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
that is read or written during an RDP access will depend
upon the current setting of the RAP. RAP serves as a
pointer into the CSR space.
CSR0: Am79C972 Controller Status and Control
Register
Certain bits in CSR0 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR0 and write back
the value just read to clear the interrupt condition.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
ERR
Error is set by the OR of CERR,
MISS, and MERR. ERR remains
set as long as any of the error
flags are true.
Read accessible always. ERR is
read only. Write operations are
ignored.
14
RES
Reserved locations. Read/Write
accessible always. Read returns
zero.
13
CERR
Collision Error is set by the
Am79C972 controller when the
device operates in half-duplex
mode and the collision inputs to
the GPSI port failed to activate
within 20 network bit times after
the chip terminated transmission
(SQE Test). This feature is a
transceiver test feature. CERR
reporting is disabled when the
GPSI port is active and the
Am79C972 controller operates in
full-duplex mode.
When the MII port is selected,
CERR is only reported when the
external PHY is operating as a
half-duplex 10BASE-T PHY.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the ERR
bit.
Read/Write accessible always.
CERR is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
CERR
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
12
MISS
Missed Frame is set by the
Am79C972 controller when it has
lost an incoming receive frame
resulting from a Receive Descrip-
tor not being available. This bit is
the only immediate indication that
receive data has been lost since
there is no current receive de-
scriptor. The Missed Frame
Counter (CSR112) also incre-
ments each time a receive frame
is missed.
When MISS is set, INTA is as-
serted if IENA is 1 and the mask
bit MISSM (CSR3, bit 12) is 0.
MISS assertion will set the ERR
bit, regardless of the settings of
IENA and MISSM.
Read/Write accessible always.
MISS is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
MISS
is
H_RESET, S_RESET, or by set-
ting the STOP bit.
cleared
by
11
MERR
Memory Error is set by the
Am79C972 controller when it re-
quests the use of the system in-
terface bus by asserting REQ
and has not received GNT asser-
tion after a programmable length
of time. The length of time in mi-
croseconds before MERR is as-
serted will depend upon the
setting of the Bus Timeout Regis-
ter (CSR100). The default setting
of CSR100 will give a MERR after
153.6
μ
s of bus latency.
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參數(shù)描述
AM79C972BKD/W 制造商:Advanced Micro Devices 功能描述:
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