參數(shù)資料
型號(hào)： AM79C975VCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
封裝： TQFP-176
文件頁(yè)數(shù)： 187/304頁(yè)
文件大小： 2092K
代理商： AM79C975VCW
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Am79C973/Am79C975
187
P R E L I M I N A R Y
TXD[3:0] nibble data path is
looped back onto the RXD[3:0]
nibble data path. TX_CLK is
looped back as RX_CLK. TX_EN
is looped back as RX_DV. CRS is
correctly OR
’
d with TX_EN and
RX_DV and always encompass-
es the transmit frame. TX_ER is
looped back as RX_ER. Howev-
er, TX_ER will not get asserted
by the Am79C973/Am79C975
controller to signal an error. The
TX_ER function is reserved for
future use.
Read/Write accessible always.
MIIILP is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit.
0
RES
Reserved location. Written as ze-
ros and read as undefined.
BCR33: PHY Address Register
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
RES
Reserved locations. Written as
zeros and read as undefined.
9-5
PHYAD
Management Frame PHY Ad-
dress. PHYAD contains the 5-bit
PHY Address field that is used in
the management frame that gets
clocked out via the MII manage-
ment port pins (MDC and MDIO)
whenever a read or write transac-
tion occurs to BCR34. The PHY
address 1Fh is not valid. The
PHY address of the internal PHY
unit is 1Eh (30 dec.)
The Network Port Manager cop-
ies
the
PHYAD
Am79C973/Am79C975 controller
reads the EEPROM and uses it to
communicate with the external
PHY. The PHY address must be
programmed into the EEPROM
prior to starting the Am79C973/
Am79C975 controller.
after
the
Read/Write accessible always.
PHYAD
is
undefined
H_RESET and is unaffected by
S_RESET and the STOP bit.
after
4-0
REGAD
Management Frame Register Ad-
dress. REGAD contains the 5-bit
Register Address field that is
used in the management frame
that gets clocked out via the inter-
nal MII management interface
whenever a read or write transac-
tion occurs to BCR34.
Read/Write accessible always.
REGAD
is
undefined
H_RESET and is unaffected by
S_RESET and the STOP bit.
after
BCR34: PHY Management Data Register
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
MIIMD
MII Management Data. MIIMD is
the data port for operations on the
MII management interface (MDIO
and MDC). The Am79C973/
Am79C975 device builds man-
agement frames using the PHY-
AD and REGAD values from
BCR33. The operation code used
in each frame is based upon
whether a read or write operation
has been performed to BCR34.
Read cycles on the MII manage-
ment interface are invoked when
BCR34 is read. Upon completion
of the read cycle, the 16-bit result
of the read operation is stored in
MIIMD. Write cycles on the MII
management interface are in-
voked when BCR34 is written.
The value written to MIIMD is the
value used in the data field of the
management write frame.
Read/Write accessible always.
MIIMD
is
undefined
H_RESET and is unaffected by
S_RESET and the STOP bit.
after
BCR35: PCI Vendor ID Register
Note:
Bits 15-0 in this register are programmable
through the EEPROM.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
VID
Vendor ID. The PCI Vendor ID
register is a 16-bit register that
相關(guān)PDF資料
PDF描述
AM79C976 PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C976 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KC 制造商:Rochester Electronics LLC 功能描述:METRIC PLASTIC QUAD-RING - Bulk
AM79C976KCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller
AM79C976KD 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC)
AM79C976KF 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP
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