參數(shù)資料
型號(hào)： AM79C984AKCW
廠(chǎng)商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： Circular Connector; No. of Contacts:6; Series:MS27474; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:8; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:8-35 RoHS Compliant: No
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 18/44頁(yè)
文件大小： 222K
代理商： AM79C984AKCW
P R E L I M I N A R Y
18
Am79C984A
Notes:
1. CRS = Carrier Sense, COL = Collision, JAB = Jabber, LINK = Link, LB = Loop Back, PAR = Partition, DIS = Port Disabled,
blk = Blink (Number = period of Blink).
2. For the LDC
0-2
setting of 000: If the port is partitioned, the LINK LED is off.
3. All LEDs blink 16 times at 260 ms per blink after reset.
4. All LEDs are on for approximately 4 seconds after reset.
5. LDC
0-2
= ‘010’ and ‘011’ are undefined.
LED software override is executed in two stages, by
first issuing the blink rate (Software Override of LED
Blink Rate) and then issuing the command to enable
the particular port LEDs (Enable Software Override of
Bank A/B LEDs). All port combinations selected for
software override control will reference the blink rate
last issued by the Software Override of the LED Blink
Rate command.
LDA
0-4
, LDB
0-4
, LDGA, and LDGB are open drain out-
put drivers that sink 12 mA of current to turn on the
LEDs. In a multiple eIMR configuration, the outputs
from the global LED drivers (LDGA and LDGB) of each
chip can be tied together to drive a single pair of global
status LEDs.
CRS and COL are extended to make it easier for visual
recognition; that is, they will remain active for some
time even if the corresponding condition has expired.
Once carrier sense is active, CRS will remain active for
a minimum of 4 ms. Once a collision is detected, COL
is active for at least 4 ms. The exception to this rule is
for selection LDC
0-2
= 111. For this selection, COL is
stretched to 100
μ
s.
When LDC
0-2
= 000 or LDC
0-2
= 001, the loopback at-
tribute (LB) for the AUI port is displayed on LDA
0
. LB is
true when DO on the MAU is successfully looped back
to DI on the AUI port. LB is false (off) if a loopback error
is detected, or if the AUI port is disabled or in the re-
verse mode. Transmit carrier sense is sampled at the
end of packet to determine the state of LB. The state of
LB remains latched until carrier sense is sampled again
for the next packet. The default/power-up state for LB is
false (off).
Figure 1 shows the recommended connection of LEDs.
When LDA
0-4
, LDB
0-4
, LDGA, or LDGB are LOW, the
LED lights.
Figure 1. Visual Monitoring Application—Direct
LED Drive
Network Activity Display
The eIMR status port can drive up to eight LEDs to in-
dicate the network-utilization level as a percentage of
bandwidth. The status port uses eight dedicated out-
puts (ACT
0-7
) to drive a series of LEDs. The number of
LEDs in the series that will be lit increases as the
amount of network activity increases. ACT
0
represents
the lowest level of activity; ACT
7
represents the high-
est. ACT
0-7
are open-drain outputs that typically sink
12 mA of current to turn on the LEDs. See Figure 2.
Table 2. LED Attribute-Monitoring Program Options
LED Control
LDC
2
LDC
1
0
0
0
0
1
Global LEDs
LDGA
CRS
CRS
TP LEDs
AUI LEDs
LDC
0
0
1
0
1
0
LDGB
COL
COL
LDA
1-4
LINK (Note 2)
LINK
LDB
1-4
PAR
CRS
LDA
0
LB
LB
LDB
0
PAR
CRS
0
0
1
1
0
Reserved (Note 5)
Reserved (Note 5)
LINK
CRS 260-ms blk
LINK (Note 3)
CRS 512-ms blk
LINK
CRS 130-ms blk
CRS 260-ms blk
COL
COL 260-ms blk
JAB
PAR
COL 260-ms blk
PAR (Note 3)
CRS 260-ms blk
(Note 3)
CRS 512-ms blk
PAR
COL 260-ms blk
PAR (Note 3)
1
0
1
1
1
0
CRS
COL
PAR or DIS
CRS 130-ms blk
PAR or DIS
1
1
1
CRS
COL
LINK (Note 4)
PAR 1.56-s blk
COL (Note 4)
(Note 4)
PAR 1.56-s blk
PAR (Note 4)
eIMR
LED
Interface
LDA[4:0]
LDB[4:0]
LDGA
LDGB
R
V
DD
Typical
20650B-6
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