參數(shù)資料
型號(hào): AM79C984AKCW
廠商: ADVANCED MICRO DEVICES INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Circular Connector; No. of Contacts:6; Series:MS27474; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:8; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:8-35 RoHS Compliant: No
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 35/44頁
文件大小: 222K
代理商: AM79C984AKCW
P R E L I M I N A R Y
Am79C984A
35
SWITCHING CHARACTERISTICS (continued)
Notes:
1. Parameter not tested.
2. DI pulses narrower than t
PWODI
(min) will be rejected; pulses wider than t
PWODI
(max) will turn internal DI carrier sense on.
3. DI pulses narrower than t
PWKDI
(min) will maintain internal DI carrier on; pulses wider than t
PWKDI
(max) will turn internal DI
carrier sense off.
4. CI pulses narrower than t
PWOCI
(min) will be rejected; pulses wider than t
PWOCI
(max) will turn internal CI carrier sense on.
5. CI pulses narrower than t
PWKCI
(min) will maintain internal CI carrier on; pulses wider than t
PWKCI
(max) will turn internal CI
carrier sense off.
6. RXD pulses narrower than t
PWKRD
(min) will maintain internal RXD carrier sense on; a pulse wider than t
PWKRD
(max) will turn
RXD carrier sense off.
Parameter
Symbol
Twisted Pair Port Timing
t
TXTD
t
TETD
t
PWKRD
Parameter Description
Test Conditions
Min
Max
Unit
CLK Rising Edge to TXD
±
Transition Delay
Transmit End of Transmission
RXD Pulse Width Maintain/Turn-off
Threshold
Idle Signal Period
Idle Link Test Pulse Width
Control Port Timing
t
SCLK
SCLK Clock Period
t
SCLKH
SCLK Clock HIGH
t
SCLKL
SCLK Clock LOW
t
SCLKR
SCLK Clock Rise Time
t
SCLKF
SCLK Clock Fall Time
t
SISET
SI Input Setup Time to SCLK Rising Edge
t
SIHLD
SI Input Hold Time from SCLK Rising Edge
t
SODLY
SO Output Delay from SCLK Rising Edge
50
375
200
ns
ns
ns
250
136
|V
IN
|>|V
THS
| (Note 6)
t
PERLP
t
PWLP
8
75
24
120
ms
ns
100
30
30
10
10
10
10
40
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 100 pF
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