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參數(shù)資料
| 型號： | AM79C989JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡接口 |
| 英文描述： | Quad Ethernet Switching Transceiver (QuEST⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 18/37頁 |
| 文件大?。?/td> | 198K |
| 代理商： | AM79C989JC |
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Am79C989
P R E L I M I N A R Y
Table 2.
QuEST Device Address Designations
Table 3.
Channel Address Designations
Interrupt Function
The Interrupt function indicates when there is a change
in the Link Status, Duplex Mode, Auto-Negotiation sta-
tus, MAU Error status, or any combination thereof for
any port. The Interrupt Register (Register 16) contains
the interrupt status and interrupt enable bits. The status
is always updated whether the interrupt enable bits are
set or not. However, if the interrupt enable bits are set
active, the logical OR of the selected bits will drive the
QINT open drain output pin.
When an interrupt occurs, the system will need to poll
the interrupt register to determine the source of the in-
terrupt and to clear the status bits. The individual regis-
ters can be read to determine the exact nature of the
change in status. Individual bits clear on read (COR)
except for the Jabber error, which is a Self-Clearing
(SC) bit when the QuEST device exits the Jabber state.
3.3 Volt Operation
The QuEST device is designed to easily and reliably in-
terface to systems with 3.3 V or 5 V power supplies.
This is accomplished by having a separate power sup-
ply pin, VDDIO, which can be connected to either a 3.3
V or 5 V supply. The only pins affected by the choice of
supply are: QRX_DATA, QRX_VALID, QRX_CRS,
QCLSN, and MDIO.
The data sheet specification for the QuEST device is
for TTL input and output levels. The QuEST device
meets these specifications, regardless of which supply
voltage is used. The difference made by using a 3.3 V
supply is that the MAXIMUM output voltage on the pins
listed above is guaranteed by design not to exceed
3.3 V.
REGISTER DESCRIPTION
The QuEST device supports nine physical registers per
port plus four registers which are globally shared
among all four ports. In summary, there are 40 registers
available.
Table 4.
Register and Port Matrix
Shared Registers
Four registers are globally shared among all four ports:
Registers 2 and 3 designate the Device ID, Register 16
is Interrupt Enable and Status, and Register 17 is Sum-
mary Status. When accessing the shared registers, the
lower two bits of the PHYAD address (bits A1 and A0)
are ignored.
PHYAD Bits
Signals with Pull up Resistors
A4
A3
A2
0
0
0
no signals
0
0
1
QCLSN
0
1
0
QRX_VALID
0
1
1
QRX_ VALID, QCLSN
1
0
0
QRX_DATA
1
0
1
QRX_DATA, QCLSN
1
1
0
QRX_DATA, QRX_ VALID
1
1
1
QRX_DATA, QRX_ VALID, QCLSN
PHYAD Bit
Channel Number
A1
A0
0
0
0
0
1
1
1
0
2
1
1
3
REGAD
Register Name
PHYAD [0:1] /Port
00
01
10
11
Port Number
0
Auto Negotiation
Control
0
1
2
3
1
Auto Negotiation
Status
0
1
2
3
2-3
Device ID
Shared
4
Auto Negotiation
Advertisement
0
1
2
3
5
Auto Negotiation Link
Partner
0
1
2
3
6
Auto Negotiation
Expansion
0
1
2
3
7
Auto Negotiation Next
Page
0
1
2
3
8-15
Unused
Unused
16
Status Change
Interrupt
Shared
17
Summary Status
Shared
18
Control
0
1
2
3
19
Status
0
1
2
3
20
Error Mask
0
1
2
3
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C989JC/T | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C989JCT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Quad Ethernet Switching Transceiver (QuEST⑩) |
| AM79C98JC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
| AM79C98JC/B | 制造商:Advanced Micro Devices 功能描述: 制造商:Advanced Micro Devices 功能描述:Part Number Only |
| AM79C98JCDV/B | 制造商:Advanced Micro Devices 功能描述: |
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