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參數(shù)資料
| 型號： | AM79C989JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Quad Ethernet Switching Transceiver (QuEST⑩) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 21/37頁 |
| 文件大小： | 198K |
| 代理商： | AM79C989JC |
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Am79C989
21
P R E L I M I N A R Y
Device ID Registers (Reg 2-3)
Device ID Registers (Reg 2-3) contain Read/Only
(R/O) bits. Registers 2 and 3 designate a unique De-
vice ID: the manufacturer ID is designated by Reg 2 bits
15:0 and Reg 3 bits 15:10; the model number is desig-
nated by Reg 3 bits 9:4; the Revision Number is desig-
nated by Reg 3 bits 3:0. This register is not duplicated
for each port.
Table 9.
Register 2
Table 10.
Register 3
Auto-Negotiation Advertisement Register (Reg 4)
The Auto-Negotiation Advertisement Register (Reg 4)
contains Read/Write (R/W) or Read/Only (R/O) bits.
This register contains the advertised ability of the
QuEST device. This register is duplicated on a per port
basis. The purpose of this register is to advertise the
technology ability to the link partner device. When this
register is modified, Restart Auto-Negotiation (Reg 0,
bit 9) must be set to advertise the change.
Table 11.
Auto-Negotiation Advertisement Register (Reg 4)
Note:
When this register is modified, Restart Auto-Negotiation (Reg 0, bit 9) must be set to advertise the change.
Bit(s)
Name
Description
Read/Write
Default/Reset
(binary)
Default/Reset
(Hex)
15:0
PHY_ID[31:16]
Bits 3-18 of the IEEE Organizationally
Unique Identifier.
R/O
0000 0000
0000 0000
0000
Bit(s)
Name
Description
Read/Write
Default/Reset
(binary)
Default/Reset
(Hex)
15:10
PHY_ID[15:10]
Bits 19-24 of the IEEE Organizationally
Unique Identifier.
R/O
01
1010
1A
9:4
PHY_ID[9:4]
QuEST Model Number
R/O
01
1111
1F
3:0
PHY_ID[3:0]
Revision Number
R/O
0000
0
Bit(s)
Name
Description
Read/
Write
Default/
Reset
15
Next Page
1 = Next page exchange requested;
0 = Next page exchange not requested.
R/W
0
14
Reserved
Written and read as zero.
R/O
0
13
Remote Fault
1 = Remote fault bit is inserted into the base link code word during
the Auto-Negotiation process;
0 = The base link code work will have the bit position for remote fault
as cleared.
R/W
0
12:11
Reserved
Written and read as zero.
R/O
0
10:7
Reserved
Written and read as zero.
R/O
0
6
Full Duplex
1 = Full Duplex capability is advertised;
0 = Full Duplex capability is not advertised.
R/W
0
5
Half duplex
1 = Half Duplex capability is advertised;
0 = Half Duplex capability is not advertised
R/W
1
4:0
Selector Field
The QuEST device is an IEEE 802.3 compliant device.
R/O
0x01
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PDF描述 |
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| AM79C989JCT | Quad Ethernet Switching Transceiver (QuEST⑩) |
| AM79C98 | Twisted-Pair Ethernet Transceiver (TPEX) |
| AM79C98JC | Twisted-Pair Ethernet Transceiver (TPEX) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C989JC/T | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C989JCT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Quad Ethernet Switching Transceiver (QuEST⑩) |
| AM79C98JC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
| AM79C98JC/B | 制造商:Advanced Micro Devices 功能描述: 制造商:Advanced Micro Devices 功能描述:Part Number Only |
| AM79C98JCDV/B | 制造商:Advanced Micro Devices 功能描述: |
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