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| 型號(hào)： | AM8530H |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 57/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530H |
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Data Communication Modes Functional Description
AMD
4–5
and provides the mechanism by which character synchronization is established at a re-
ceiver. Since data between flags may contain the flag pattern, the sequence of six con-
secutive one bits is prevented from occurring through a process called zero-bit insertion,
in which the transmitter inserts a zero bit after any five consecutive one bits. Likewise, the
receiver deletes any zero bit that follows five consecutive one bits in the bit stream be-
tween the opening and closing flag of a frame.
SYNC
DATA
CRC
Figure 4–2. MONOSYNC Format
SYN
HEADER
TEXT
EXT
OR
ETB
BCC
SYN
SOH
STX
DIRECTION OF SERIAL DATA FLOW
BCC = Block Checking Calculation
Figure 4–3. BISYNC Format
BEGINNING
FLAG
01111110
8 BITS
ADDRESS
8 BITS
FRAME
CHECK
16 BITS
CONTROL
8 BITS
INFORMATION
ANY NUMBER
OF BITS
FRAME
ENDING
FLAG
01111110
8 BITS
Figure 4–4. SDLC/HDLC Frame Format
The Frame Check Sequence (FCS) is 16 bits long and contains the generated CRC for
the frame. All data transmitted between the opening and closing flags (excluding inserted
zeros) are included in the CRC calculation. The generator polynomial used in SDLC is the
CCITT polynomial, X
16
+ X
12
+ X
5
+ 1.
Since the information field may contain any number of bits and not necessarily an integral
number of 8-bit characters, the end of a frame is determined by counting back 16 bits
from the closing flag of a frame.
In the sections that follow, the term “Synchronous mode(s)” will be used to refer to either
BISYNC and/or MONOSYNC modes, and SDLC mode will be used when referring to nor-
mal SDLC operation. SDLC Loop mode will be referred to as either Loop mode or SDLC
Loop mode.
4.3
The mode that an SCC channel operates in is selected by programming WR4 as shown
below. Note that the ‘x’s indicate a don’t care condition (i.e., bit setting are ignored by
SCC) and ‘’s indicate programmable settings.
MODE S ELECT ION
Note that bits D7 and D6 of WR4 are ignored in SDLC and Synchronous modes because
the x1 clock is forced internally.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
| AM85C30-16JC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530H/AM85C301992 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller |
| AM8530H-4DC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530H-4DCB | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
| AM8530H-4JC | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Communications Controller |
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