參數(shù)資料
型號(hào): AM8530H
廠商: Advanced Micro Devices, Inc.
英文描述: Serial Communications Controller
中文描述: 串行通信控制器
文件頁(yè)數(shù): 85/194頁(yè)
文件大小: 797K
代理商: AM8530H
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)當(dāng)前第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)
Data Communication Modes Functional Description
AMD
4–33
via bit D4 in WR3. The Enter Hunt Mode bit in WR3 is a command so writing a ‘0’ to it has
no effect.
In Synchronous modes, once character synchronization has been established, Hunt
mode is terminated and must remain so until the end of message has been received. At
this point, the Enter Hunt Mode command can be re-issued for the next message. Issuing
this command prematurely can lead to false character synchronization. Thus, the SYNC/
HUNT status bit in RR0 will be set only when the Enter Hunt Mode command is issued.
The Hunt status of the Receiver is reported in the SYNC/HUNT status bit in RR0 (D4).
This status bit is one of the possible sources of External/Status interrupts, with both tran-
sitions causing an interrupt. This is true even if the SYNC/HUNT bit is set as a result of
the processor issuing the Enter Hunt Mode command.
While in Hunt mode, the receiver path used in establishing character synchronization will
depend on the mode selected. In either case, however, synchronization will be estab-
lished at the beginning of each transmission either through a two character (BISYNC) or a
single character (MONOSYNC) synchronizing pattern. When character synchronization is
established Hunt mode is terminated and the receiver stops scanning the communication
line for the synchronizing pattern. At this point data passes to the Receive Shift Register
and characters are formed by assembling the proper number of consecutive bits following
the synchronizing pattern before being transferred into the Receive Data FIFO.
4.10.1.1
In Synchronous modes, except External SYNC mode, if bit D7 of WR11 is set to ‘0’, the
SYNC pin will be configured as an output and the SCC will drive it Low every time a sync
character is detected in the data stream. Note, however, that the SYNC pin is activated
regardless of character boundaries so any external circuitry using it in Synchronous
modes should respond only to the SYNC pulse that occurs while the receiver is in Hunt
mode. The timing for the SYNC signal is shown in Figure 4–20.
SYNC Detect Output
4.10.1.1.1
The message format for MONOSYNC is shown in Figure 4–21. In this mode, the incom-
ing data are clocked into the Receive Sync Register and compared with the contents of
WR7 on a bit-by-bit basis until a sync character is found. When a sync character is found,
character synchronization is established and data passes to the Receive Shift Register.
MONOSYNC Mode
In this mode, WR6 is always used to open a message being transmitted, and as time fill
when the transmitter has nothing to send.
4.10.1.1.2
The BISYNC message format is shown in Figure 4–22. In this mode, the synchronization
procedure is similar to that of MONOSYNC except that two sync characters are used for
character synchronization instead of one. In this mode, incoming data are shifted into the
Receive Shift Register while the next eight bits are assembled in the Receive Sync Regis-
ter. If these two characters match the programmed characters in WR6 and WR7, respec-
tively, synchronization is established and the incoming data bypasses the Receive Sync
Register and enters the 3-bit delay directly.
BISYNC Mode
In this mode, the concatenation of WR6 with WR7 is always used during transmit and re-
ceive operations.
相關(guān)PDF資料
PDF描述
AM85C30-10PC Enhanced Serial Communications Controller
Am85C30 Serial Communications Controller
AM85C30 Enhanced Serial Communications Controller
AM85C30-8PC Enhanced Serial Communications Controller
AM85C30-16JC Enhanced Serial Communications Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM8530H/AM85C301992 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am8530H/Am85C30 1992 - Am8530H/Am85C30 Serial Communications Controller
AM8530H-4DC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM8530H-4DCB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM8530H-4JC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller