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參數(shù)資料
| 型號： | AMIS-710616-AS |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 圖像傳感器 |
| 英文描述： | IMAGE SENSOR-CMOS, 3V |
| 文件頁數(shù)： | 14/19頁 |
| 文件大小： | 954K |
| 代理商： | AMIS-710616-AS |
AMIS-710616-AS: CIS PCB
Data Sheet
Product Specification
(11) Modulation transfer function depends on the optical system. Since this system relies on the users optical system, it was not measured. Referring back to Note
5, measurements on Up, all notes that reference the optical measurements apply to MTF measurements as well. Using a conservative engineering estimate,
the sensor’s MTF is in excess of 70 percent at the optical Nyquest frequency.
7.0 Electrical Timing Characteristics
7.1 Clock Amplitude and Duty Characteristics
Table 7-1: Clock Amplitude and Duty Characteristics
(Ta =25
°C)
Specification
Item
Symbol
Condition
Min.
Typ.
Max.
Units
VIH
(1)
Clock input voltage
VIL
(1)
For values see
the notes
See Note (1) for values
IIH
(1)
Clock input current
IIL
(1)
See Note (1) for values
Clock frequency
Freq
(2)
0.100
5.0
6.0
MHz
Line read time
Tint
(3)
160
192
1000
s
Clock pulse duty cycle
Ratio = tw/ to
(4)
25
50
75
%
Notes:
(1)
These CP and SP values are compatible with CMOS 74HCXX series logic devices.
(2)
Freq is not only the clock frequency, but is also equal to the pixel sample rate. See not 2 under Table 6.1.
(3)
Tint is the line scan read time, which depends on the interval between the SP entries. See Note 1 under Table 6.1. The longest integration time is determined
by the degree of leakage current degradation that can be tolerated by the system. A 10ms maximum is a typical rule-of-thumb. An experienced CIS user can
use his discretion to determine the desired tolerance level for the given system.
(4)
The definition for the symbols used in the ratio is defined in Section 7.2.
7.2 Clock Timing Characteristics
This table defines the symbols used in the timing diagram (Figure 3). It is for a single video section, however it applies to all eight video
sections. Accordingly, the system-timing diagram is a composition of this timing diagram repeated eight times, with all waveforms in
parallel, so electrically the system produces pixels from all eight video sections simultaneously.
Table 7-2: Clock Timing Characteristics
Item
Symbol
Min.
Typ.
Max.
Units
Clock cycle time
(2)
to
0.1666
0.200
10
s
Clock pulse width
(2)
tw
0.100
ns
Clock duty cycle
(2)
duty
25
50
75
%
Prohibit crossing time of SP
tprh
30
ns
Data setup time
tds
30
ns
Data hold time
tdh
25
ns
Signal delay time
tdl
75
ns
Signal sample time
tsmp
(3)
125
ns
Signal fall time
tsigf
75
ns
Recommended SP generation
Tonoff
(4)
Notes:
(1)
This applies to the whole chart. All of the symbol definitions in Table 7-2 are used in Figure 3. For the complete system, there are only two clocks, CP and SP and
their logic levels are compatible with CMOS 74HCXX series logic devices.
(2)
See the notes on clock periods (the inverse of freq) and their duty cycles under Table 5-1 Notes 3 and 4.
(3)
See AMIS-720639 data sheet Page 6, Table 6A, Note 6.
(4)
This is the recommended method for SP generation because the shift register loads only on the falling edge.
4
AMI Semiconductor – July 06, M-20595-001
www.amis.com
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