參數(shù)資料
型號: AN231K04-DVLP3
廠商: Electronic Theatre Controls, Inc.
英文描述: Dynamically Reconfigurable dpASP
中文描述: 動態(tài)可重構(gòu)dpASP
文件頁數(shù): 13/24頁
文件大?。?/td> 445K
代理商: AN231K04-DVLP3
AN231E04 Datasheet – Dynamically Reconfigurable dpASP
DS231000-U001d
- 13 -
1.5.6
Parameter
Division ratio Primary divider
Division ratio secondary divider
Division ratio auto zero clock
Min clock speed
Clock Dividers
Symbol
DIV
RATIOPR
DIV
RATIOSEC
DIV
AZ
Min
1
1
1000
Typ
-
-
162K
1kHz @
25°C)
10kHz @
85°C
Max
510
510
510K
Unit
-
-
-
Comment
Software controlled.
Software controlled.
Typical is default value.
Each CAM has a different lower
clock frequency depending on the
parameters set. Excessively low
clock frequency will cause signal
droop.
Each CAM has a different upper
clock frequency depending on the
parameters set. Excessively high
clock frequency will cause poor
settling and loss of precision.
Measured in terms of cycles of
clock from a primary clock divider.
CLK
MIN
-
-
KHz
Max clock speed
CLK
MAX
-
-
8
MHz
Phase delay
Phase
D
0
-
255
cycles
1.5.7
Parameter
Intrinsic Porb duration
Porb brown out voltage
PORb & Auto-null
Symbol
Porb
DEL
Min
0.5
Typ
1
Max
2
Unit
ms
Comment
After release of Porb pin.
Porb will reset device if VDD drops
below this level to prevent RAM
corruption.
Duration for AZ cycle of opamps
Porb
BROWN
0.8
1.1
1.5
V
Auto-null period
5
AZ
DEL
-
60
-
ms
1.5.8
Parameter
VMR Output Voltage
VREF+ Output Voltage
VREF- Output Voltage
VMR (voltage Mid Rail) and VREF (Reference Voltage) Ratings
Symbol
Vvmr
Vref+
Vref-
Min
1491
2469
481
Typ
1500
2492
501
Max
1509
2515
520
Unit
mV
mV
mV
Comment
At 25°C, VDD=3.3 volts, see figure 3
At 25°C, VDD=3.3 volts, see figure 4
At 25°C, VDD=3.3 volts, see figure 4
Over process and supply voltage
corners
Over process and supply voltage
corners
Output Voltage Deviation VMR
Vrefout
-
0.5
1.0
%
Output Voltage Deviation
VREF+, VREF-
Voltage Temperature
Coefficient
VREF+, VMR, VREF-
Power Supply Rejection Ratio,
VMR
Power Supply Rejection Ratio
Vref+ and Vref-
Vrefout
-
1.0
2.0
%
Vreftc
-
-
-
-
See typical graphical data below
-40°C to 125°C
PSSR
TBD
-
-
dB
DC
PSSR
TBD
-
-
dB
DC
Start Up Time
5
see application note AN231002 “Auto-nulling within the AN231E04”
Tstart
-
-
1
ms
Assuming recommended
capacitors, 25°C, VDD=3.3 volts
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