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參數(shù)資料
| 型號： | AN231K04-DVLP3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dynamically Reconfigurable dpASP |
| 中文描述： | 動態(tài)可重構(gòu)dpASP |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 445K |
| 代理商： | AN231K04-DVLP3 |
AN231E04 Datasheet – Dynamically Reconfigurable dpASP
DS231000-U001d
- 15 -
1.5.9
Parameter
Output Range
CAB (Configurable Analog Block) Differential Operational Amplifier
Symbol
Min
Typ
Max
Unit
Comment
GainInv 1kHz THD > -80dB.
Common mode voltage = 1.5 V
Limited by signal clipping.
GainInv THD exceeds -80dB
Common mode voltage = 1.5 V
VMR set to 1.5V
Vinouta
0.05
-
2.95
V
Differential Output voltage
Vdiffioa
-
-
+/-2.9
V
Common Mode Input Voltage
Range
6
Common Mode
Voltage Deviation
Equivalent Input Voltage Offset.
Equivalent Input Voltage Offset.
Equivalent Input Voltage Offset.
Offset Voltage Temperature
Coefficient
Offset Voltage Temperature
Coefficient
Vcm
1.4
1.5
1.6
V
VcmD
0
-
+/-50
mV
Deviation is caused by opamp
common mode offset voltages.
Intrinsic offset voltage.
Auto-null offset voltage.
Auto-null & chopped offset
Auto-null mode, from -40°C to
125°C.
Auto-null and chopped mode,
from -40°C to 125°C.
DC. Variation between CAMs is
expected because of variations
in architecture.
GainInv CAM, clock = 1MHz,
gain = 1. -20dBu input at 1kHz
See figure 6
Applicable when the OpAmp
load is internal to the dpASP
Applicable when the OpAmp
driving signal out of the dpASP
package. Routing resistance
causes degradation from Slew
Applicable when sourcing and
loading the OpAmp with a load
internal to the dpASP. CAMs
limit signal frequency to a lower
value. See figure 5
The OpAmp output is designed
to drive all internal nodes, these
are dominantly capacitive loads
Output to a dpASP output pin
(output cell bypass mode). This
variable is influenced by CAB
capacitor size, CAB clock
frequency and CAB architecture
Unity-gain GainHold CAM,
1MHz clocking. Idle channel.
Unity-gain GainHold CAM,
1MHz clocking. 0dBu input at
1KHz, Noise and distortion
summed from 22Hz to 22KHz
Unity-gain GainHold CAM and
SnH output cell. 1MHz clocking.
0dBu input at 1KHz. See figure 7
VoffsetI
VosAZ
VosAZchpI
-
-
-
3
18
1000
250
mV
uV
uV
250
75
see
graph
VosAZ
-
19
μV/°C
VosAZChp
-
-
< 0.1
μV/°C
Power Supply Rejection Ratio
PSSR
-
60
-
dB
Common Mode Rejection Ratio
CMRR
-
54
-
dB
Differential Slew Rate, Internal
SlewI
-
35
-
V/μsec
Differential Slew Rate, External
SlewE
-
30
-
V/μsec
Unity Gain Bandwidth,
Full Power Mode.
UGB
-
18
-
MHz
Input Impedance, Internal
Rin
10
-
-
Mohm
Output Impedance, Internal
Rout
-
-
-
Ohms
Output Impedance, External
Rout
-
600
-
Ohms
Output Load, External
7
Output Load, External
Input Referred Noise Floor
8
Rload
Cload
1
-
-
-
-
Kohm
pF
100
IRN
-
300
-
nV/
√
Hz
Signal-To Noise and Distortion
Ratio
SINAD
-
86
-
dB
Spurious Free Dynamic Range
8
SFDR
-
100
-
dB
6
The is for the OpAmp. The use of virtual earth architectures means the CAMs can exceed these values
7
The maximum load for an analog output is 100 pF || 1 K Ohms. This load is with respect to AVSS. Using the DPASP with CAB
Opamps driving directly off chip is not recommended. Full characterization of the performance of each application circuit by the
designer is necessary
8
Using an I/O Cell Sample & Hold is used to prevent the variable routing resistance affecting the harmonic response
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