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參數(shù)資料
| 型號： | AND8066D |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Interfacing with ECLinPS |
| 中文描述： | 接口與業(yè)界的EClinPS |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 72K |
| 代理商： | AND8066D |
Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 2
1
Publication Order Number:
AND8066/D
AND8066/D
Interfacing with ECLinPS
Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering
STANDARD ECL INTERFACE: DIFFERENTIAL
DRIVER AND RECEIVER
A typical Emitter Coupled Logic (ECL) circuit interface
may be defined as a differential driver device sending a paired
set of commentary signals – True and Invert – over a pair of
standard, controlled impedance lines to an ECL differential
receiver device. A typical ECL output line driver consists of
a bipolar transistor in an Emitter Follower configuration with
the collector at V
CC
power supply rail and the emitter pinned
out. A standard, typical differential ECL receiver consists of
a pair of bipolar transistors in a differential configuration with
the True and Invert signals providing base drives to the two
base inputs. Proper differential levels are specified as V
pp
and
V
IHCMR
. When an input is interconnected as a differential
signal, the DC Single Ended parameters of V
IL
and V
IH
do not
apply. Terminations are required to preserve optimum signal
integrity, as shown in Figure 1. The standard, controlled
impedance lines assume a sufficient return current capability.
V
EE
V
CC
V
EE
V
TT
V
CC
Figure 1. Standard Differential ECL Interconnect
Q
Q
Q
Q
D
D
True
Invert
SINGLE–ENDED INTERFACE
Signals may be imported as full differential lines or as a
Single–Ended (SE) line interconnection. The SE
interconnection may be seen as a special variation of the
typical differential interface using only one driver source
trace line. This single trace line drives a (Base) input pin of
the receiver, as shown in Figure 2. Although a receiver may
present only a single, dedicate SE input pin instead of a
differential input pair of pins, such a receiver still would have
a differential structure with the unavailable input controlled
by internal circuitry.
V
EE
V
CC
V
EE
Figure 2. Standard Single–Ended ECL Interconnect
True
V
TT
V
CC
Single–ended receiver input levels are specified in data
sheets DC CHARACTERISTICS block as V
IH
and V
IL
Parameters. Each temperature has a minimum and
maximum limit pair to V
IH
and V
IL
parameters, thus
defining the Single–Ended input swing, V
pp
(SE). The
V
pp
(SE) ranges from 595 mV to 890 mV, depending on the
temperature and family. The V
pp
(SE) limits constitute the
receiver device’s input single–ended sensitivity.
Both output lines of the typical differential output may
drive two independent single–ended receivers separately (see
Figure 3).
V
EE
V
CC
V
EE
Figure 3. Differential Driver with Independent
Standard Single–Ended Receivers
True
V
TT
V
CC
Invert
V
EE
V
CC
V
TT
Q
Q
Q
Q
APPLICATION NOTE
http://onsemi.com
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