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參數(shù)資料
| 型號(hào)： | APA075-TQG144I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 78/178頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA PROASIC+ 75K 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | ProASICPLUS |
| RAM 位總計(jì)： | 27648 |
| 輸入/輸出數(shù)： | 107 |
| 門(mén)數(shù)： | 75000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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ProASICPLUS Flash Family FPGAs
v5.9
4-1
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
Changes in current version (v5.9)
Page
v5.8
(June 2009)
The –F speed grade is no longer supported and was removed from the datasheet.
N/A
A note regarding RoHS compliant packages was added to the "Device Resources" table.
v5.7
(September 2008)
The "PLL Electrical Specifications" table was updated significantly. Changes were made to the
Input, VCO (Voltage Controlled Oscillator), and Output frequencies, and the acquisition time.
Table 2-10 PLL I/O Constraints is new.
Applies to Commercial and Industrial Temperature Only is the same table that was in v5.7, but it
now only applies to commercial and industrial temperature ranges. Table 2-24 DC Electrical
have been made to the drive currents at which 3.3 V VOH and VOL voltage levels are measured
changed from 0.8 V to 0.7 V for 3.3 V Schmitt-trigger input operation.
v5.6
(August 2008)
changed back to the data in v5.5.
v5.5
(February 2007)
Only.
v5.4
(October 2006)
A statement about single cell and cascaded cell timing diagrams was added to the "Enclosed
The following pins were updated in the "144-FBGA Pin" table:
Pin Number Updated Function
C2
I/O / GL1
F1
I/O / GL2
v5.3
The heading, MIL-STD-883B, and note 4 were added to the "Device Resources" table.
(May 2006)
The "Temperature Grade Offerings" table was updated to include the military (M) temperature
grade in the following device/packages:
APA300-FG144
APA300-FG256
APA600-FG256
APA600-FG484
APA600-FG676
APA1000-FG896
v5.2
90° and 270° phase shift support was removed from the datasheet.
N/A
(December 2005)
The "Ordering Information" section was updated to include RoHS information.
The last paragraph of the "Boundary Scan (JTAG)" section was updated.
The Output Frequency Range in the "Timing Control and Characteristics" section.
The title for Table 2-19 Military Temperature Grade Product Performance Retention was
updated.
The caption was updated in Figure 2-45 FIFO Reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| APA075-TQ144I | IC FPGA PROASIC+ 75K 144-TQFP |
| ABC43DRYH-S93 | CONN EDGECARD 86POS DIP .100 SLD |
| A42MX09-PLG84A | IC FPGA MX SGL CHIP 14K 84-PLCC |
| ESC65DRTS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
| EMC49DRAS | CONN EDGECARD 98POS R/A .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| APA075-TQGB | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-TQGES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-TQGI | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-TQGM | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
| APA075-TQGPP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC Flash Family FPGAs |
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