ProASICPLUS Flash Family FPGAs 2- 52 v5.9 Table 2-48 Recommended Operati" />
參數(shù)資料
型號: APA300-CQ352B
廠商: Microsemi SoC
文件頁數(shù): 138/178頁
文件大小: 0K
描述: IC FPGA PROASIC+ 300K 352-CQFP
標準包裝: 1
系列: ProASICPLUS
RAM 位總計: 73728
輸入/輸出數(shù): 248
門數(shù): 300000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
封裝/外殼: 352-BFCQFP,帶拉桿
供應商設(shè)備封裝: 352-CQFP(75x75)
ProASICPLUS Flash Family FPGAs
2- 52
v5.9
Table 2-48 Recommended Operating Conditions
Parameter
Symbol
Limits
Commercial/Industrial
Military/MIL-STD-883
Maximum Clock Frequency*
fCLOCK
180 MHz
Maximum RAM Frequency*
fRAM
150 MHz
Maximum Rise/Fall Time on Inputs*
Schmitt Trigger Mode (10% to 90%)
Non-Schmitt Trigger Mode (10% to
90%)
tR/tF
N/A
100 ns
10 ns
Maximum LVPECL Frequency*
180 MHz
Maximum TCK Frequency (JTAG)
fTCK
10 MHz
Table 2-49 Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25°C
Type
Trig. Level
Rising Edge (ns)
Slew Rate (V/ns)
Falling Edge (ns)
Slew Rate (V/ns)
PCI Mode
OB33PH
10%-90%
1.60
1.65
1.60
Yes
OB33PN
10%-90%
1.57
1.68
3.32
0.80
No
OB33PL
10%-90%
1.57
1.68
1.99
1.32
No
OB33LH
10%-90%
3.80
0.70
4.84
0.55
No
OB33LN
10%-90%
4.19
0.63
3.37
0.78
No
OB33LL
10%-90%
5.49
0.48
2.98
0.89
No
OB25LPHH
10%-90%
1.55
1.29
1.56
1.28
No
OB25LPHN
10%-90%
1.70
1.18
2.08
0.96
No
OB25LPHL
10%-90%
1.97
1.02
2.09
0.96
No
OB25LPLH
10%-90%
3.57
0.56
3.93
0.51
No
OB25LPLN
10%-90%
4.65
0.43
3.28
0.61
No
OB25LPLL
10%-90%
5.52
0.36
3.44
0.58
No
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