ProASICPLUS Flash Family FPGAs v5.9 2-55 Synchronous SRAM Read, Access Timed Out" />
參數(shù)資料
型號: APA600-BGG456
廠商: Microsemi SoC
文件頁數(shù): 141/178頁
文件大小: 0K
描述: IC FPGA PROASIC+ 600K 456-PBGA
標準包裝: 24
系列: ProASICPLUS
RAM 位總計: 129024
輸入/輸出數(shù): 356
門數(shù): 600000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-PBGA(35x35)
ProASICPLUS Flash Family FPGAs
v5.9
2-55
Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 2-28 Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Table 2-52 TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS
7.5
ns
OCH
Old DO valid from RCLKS
3.0
ns
RACH
RADDR hold from RCLKS
0.5
ns
RACS
RADDR setup to RCLKS
1.0
ns
RDCH
RDB hold from RCLKS
0.5
ns
RDCS
RDB setup to RCLKS
1.0
ns
RPCA
New RPE access from RCLKS
9.5
ns
RPCH
Old RPE valid from RCLKS
3.0
ns
RADDR
RPE
DO
RCLKS
RBD, RBLKB
New Valid Data Out
Cycle Start
Old Data Out
New Valid
Address
tRACS
tRDCS
tRDCH
tRACH
tOCH
tRPCH
tCMH
tOCA
tRPCA
tCCYC
tCML
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