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參數資料
| 型號： | AT24C08SC-09BT |
| 廠商： | ATMEL CORP |
| 元件分類： | PROM |
| 英文描述： | 1K X 8 I2C/2-WIRE SERIAL EEPROM, XMA8 |
| 封裝： | SMART CARD MODULE-8 |
| 文件頁數： | 12/14頁 |
| 文件大?。?/td> | 272K |
| 代理商： | AT24C08SC-09BT |
AT24C01ASC/02SC/04SC/08SC/16SC
7
Device Addressing
The 1 K, 2K, 4K, 8K a nd 16 K EEPROM de vices a ll
require an 8-bit device address word following a start con-
dition to enable the chip for a read or write operation (refer
to Figure 1).
The device address word consists of a mandatory one,
zero, one, zero sequence for the first four most significant
bits as shown. This is common to all the serial EEPROM
devices.
The next 3 bits of the device address word are the most
significant data word address bits for the AT24C16SC
(16K), which requires a total of 11 address bits. The
AT24C08SC (8K) requires only 10 total word address bits.
The most significant 2 bits are included in the device
address word. The unused bit of the device address word
should be set to “0”. The AT24C04SC (4K) requires only 9
total data word address bits. The most significant bit is
included in the device address word. The 2 unused bits of
the device address word should be set to “0”. The
AT24C02SC (2K) and AT24C01ASC (1K) do not require
any address bits in the device address word. The 3 unused
bits of the device address word should be set to “0”.
The eighth bit of the device address is the read/write opera-
tion select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero (ACK). If a successful compare is not made,
the chip will return to a standby state (NO ACK).
Write Operations
BYTE WRITE: A write operation requires an 8-bit data
word address following the device address word and
acknowledgment. Upon receipt of this address, the
EEPROM will again respond with a zero (ACK) and then
clock in the first 8-bit data word. Following receipt of the 8-
bit data word, the EEPROM will output a zero (ACK) and
the addressing device, such as a microcontroller, must
terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally-timed write cycle,
t
WR, to the nonvolatile memory. All inputs are disabled
during this write cycle and the EEPROM will not respond
until the write is complete (refer to Figure 2).
PAGE WRITE: The 1K/2K EEPROM is capable of an
8-byte page write, and the 4K, 8K and 16K devices are
capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
troller can transmit up to 7 (1K/2K) or 15 (4K, 8K, 16K)
more data words. The EEPROM will respond with a zero
(ACK) after each data word received. The microcontroller
must terminate the page write sequence with a stop condi-
tion (refer to Figure 3).
The data word address lower 3 (1K/2K) or 4(4K, 8K, 16K)
bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incre-
mented, retaining the memory page row location. When the
word address, internally generated, reaches the page
boundary, the following byte is placed at the beginning of
the same page. If more than 8 (1K/2K) or 16 (4K, 8K, 16K)
data words are transmitted to the EEPROM, the data word
address will “roll over” and previous data will be overwrit-
ten.
ACKNOWLEDGE POLLING: Once the internally timed
write cycle has started and the EEPROM inputs are dis-
abled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address
word. The read/write bit is representative of the operation
desired. Only if the internal write cycle has completed will
the EEPROM respond with a zero (ACK), allowing the read
or write sequence to continue.
Read Operations
Read operations are initiated the same way as write opera-
tions, with the exception that the read/write select bit in the
device address word is set to one. There are three read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS READ: The internal data word
address counter maintains the last address accessed dur-
ing the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. The address “rollover” during
read is from the last byte of the last memory page to the
first byte of the first page. The address “rollover” during
write is from the last byte of the current page to the first
byte of the same page.
Once the device address with the read/write select bit set
to “1” is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The
microcontroller does not respond with an input zero, but
does generate a following stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte
write sequence to load in the data word address. Once the
device address word and data word address are clocked in
and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out
the data word. The microcontroller does not respond with a
zero (NO ACK) but does generate a following stop condi-
tion (refer to Figure 5).
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相關代理商/技術參數 |
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|---|---|
| AT24C08SC-09BT-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C08SC-09CT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C08SC-09CT-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C08SC-09DT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| AT24C08SC-09DT-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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