參數(shù)資料
型號: AT32AP7001-ALUT
廠商: Atmel
文件頁數(shù): 20/65頁
文件大?。?/td> 0K
描述: IC MCU 32BIT AVR32 208-LQFP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標準包裝: 180
系列: AVR®32 AP7
核心處理器: AVR
芯體尺寸: 32-位
速度: 150MHz
連通性: EBI/EMI,I²C,MMC,PS2,SPI,SSC,UART/USART,USB
外圍設(shè)備: AC'97,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 90
程序存儲器類型: ROMless
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: D/A 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-LQFP
包裝: 托盤
配用: ATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMR
ATNGW100-ND - KIT AVR32 NETWORK GATEWAY
ATSTK1000-ND - KIT STARTER FOR AVR32AP7000
27
32015G–AVR32–09/09
AT32AP7001
8.4
Vector Multiplication Unit (VMU)
Each VMU consists of three multipliers used for multiplying unsigned 8-bit pixel components with
signed 12-bit coefficients.The result from each multiplication is a 20-bit signed number that is
input to a 22-bit vector adder along with an offset as shown in Figure 8-2 on page 27. The oper-
ation is equal to the offsetted vector multiplication given in the following equation:
Figure 8-2.
Inside VMUn (n
∈ {0,1,2})
8.5
Input Pixel Selector
The Input Pixel Selector uses the ISM (Input Selection Mode) field in the CONFIG register and
the three input pixel source addresses given in the PICO operation instructions to decide which
pixels to select for inputs to the VMUs.
8.5.1
Transformation Mode
When the Input Selection Mode is set to Transformation Mode the input pixel source addresses
INx, INy and INz directly maps to three pixels in the INPIXn registers. These three pixels are
then input to each of the VMUs. The following expression then represents what is computed by
the VMUs in Transformation Mode:
8.5.2
Horizontal Filter Mode
In Horizontal Filter Mode the input pixel source addresses INx, INy and INz represents the base
pixel address of a pixel triplet. The pixel triplet {IN(x), IN(x+1), IN(x+2)} is input to VMU0, the
pixel triplet {IN(y), IN(y+1), IN(y+2)} is input to VMU1 and the pixel triplet {IN(z), IN(z+1), IN(z+2)}
vmu_out
coeff0 coeff1 coeff2
vmu_in0
vmu_in1
vmu_in2
offset
+
=
Multiply
Vector Adder
Multiply
VMUn
offsetn
coeffn_1
coeffn_2
coeffn_0
vmun_in0
vmun_in1
vmun_in2
vmun_out
VMU0_OUT
VMU1_OUT
VMU2_OUT
COEFF0_0 COEFF0_1 COEFF0_2
COEFF1_0 COEFF1_1 COEFF1_2
COEFF2_0 COEFF2_1 COEFF2_2
INx
INy
INz
OFFSET0 or VMU0_OUT
OFFSET1 or VMU1_OUT
OFFSET2 or VMU2_OUT
+
=
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