參數(shù)資料
型號: AT32UC3A0512
廠商: Atmel Corp.
英文描述: AVR32 32-Bit Microcontroller
中文描述: AVR32 32位微控制器
文件頁數(shù): 19/109頁
文件大?。?/td> 10824K
代理商: AT32UC3A0512
22
AT32UC3A
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the
LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the
CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory
range allocated to it, and data transfers are performed using regular load and store instructions.
Details on which devices that are mapped into the local bus space is given in the device-specific
“Peripherals” chapter of this data sheet.
Figure 9-1 on page 22 displays the contents of AVR32UC.
Figure 9-1.
Overview of the AVR32UC CPU
9.2.1
Pipeline Overview
AVR32 UC is a pipelined processor with three pipeline stages. There are three pipeline stages,
Instruction Fetch (IF), Instruction Decode (ID) and Instruction Execute (EX). The EX stage is
split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) sec-
tion and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 9-2 on page 23 shows an overview of the AVR32 UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
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High Speed Bus master
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CPU Local
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Data memory controller
32058K
AVR32-01/12
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