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參數(shù)資料
| 型號： | AT40K40LV-3FQC |
| 廠商： | ATMEL CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 40000 GATES, PQFP304 |
| 封裝： | PLASTIC, QFP-304 |
| 文件頁數(shù)： | 29/67頁 |
| 文件大?。?/td> | 1589K |
| 代理商： | AT40K40LV-3FQC |
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35
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL.
Clocks and Reset Input buffers are measured from a V
IH of 1.5V at the input pad to the internal VIH of 50% of VCC.
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
Cell Function
Parameter
Path
Device
-3
Units
Notes
Global Clocks and Set/Reset
GCK Input Buffer
t
PD
(Maximum)
pad -> clock
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
1.3
1.5
1.6
1.9
ns
Rising edge clock
FCK Input Buffer
t
PD
(Maximum)
pad -> clock
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
0.7
0.8
0.9
ns
Rising edge clock
Clock Column Driver
tPD
(Maximum)
clock -> colclk
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
1.5
1.8
2.0
2.5
ns
Rising edge clock
Clock Sector Driver
t
PD
(Maximum)
colclk -> secclk
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
1.0
ns
Rising edge clock
GSRN Input Buffer
tPD
(Maximum)
pad -> GSRN
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
4.5
5.4
6.3
8.2
ns
Global Clock to Output
tPD
(Maximum)
clock pad -> out
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
13.0
13.4
13.8
14.5
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Fast Clock to Output
t
PD
(Maximum)
clock pad -> out
AT40K05LV
AT40K10LV
AT40K20LV
AT40K40LV
12.4
12.7
13.0
13.5
ns
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
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相關代理商/技術參數(shù) |
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| AT40K40LV-3FQI | 功能描述:IC FPGA 3.3V 2304 CELL 304PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:AT40K/KLV 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
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