參數(shù)資料
型號(hào)： AT40KEL040KZ1SB
廠商： ATMEL CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 2304 CLBS, 50000 GATES, PQFP256
封裝： MQFP-256
文件頁(yè)數(shù)： 10/42頁(yè)
文件大小： 670K
代理商： AT40KEL040KZ1SB
18
AT40KEL040
4155G–AERO–05/05
I/O Structure
AT40K has registered I/Os and group enable every sector for tri-states on obuf’s.
Pad
The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os
have pads: the ones without pads are called Unbonded I/Os. The number of unbonded
I/Os varies with the device size and package. These unbonded I/Os are used to perform
a variety of bus turns at the edge of the array.
Pull-up/Pull-down
Each pad has a programmable pull-up and pull-down attached to it. This supplies a
weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate
the signal level of the pad pin.
The input stage of each I/O cell has a number of parameters that can be programmed
either as properties in schematic entry or in the I/O Pad Attributes editor in IDS.
CMOS
The threshold level is a CMOS-compatible level.
Schmitt
A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenera-
tive comparator circuit that adds 1V hysteresis to the input. This effectively improves the
rise and fall times (leading and trailing edges) of the incoming signal and can be useful
for filtering out noise.
Delays
The input buffer can be programmed to include four different intrinsic delays as specified
in the AC timing characteristics. This feature is useful for meeting data hold require-
ments for the input signal.
Drive
The output drive capabilities of each I/O are programmable. They can be set to FAST,
MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability
(16 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive
(12 mA at 5V) buffer, while SLOW yields a standard (4 mA at 5V) buffer.
Tri-State
The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open
drain (0 or Z) by programming an I/O’s Source Selection mux. Of course, the output can
be normal (0 or 1), as well.
Source Selection Mux
The Source Selection mux selects the source for the output signal of an I/O. See
Figure 12 on page 21.
Primary, Secondary and
Corner I/Os
The AT40KEL040 has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O.
Every edge cell except corner cells on the AT40KEL040 has access to one Primary I/O
and two Secondary I/Os.
Primary I/O
Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and
from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It
also connects into the repeaters on the row immediately above and below the adjacent
core cell. In addition, each Primary I/O also connects into the busing network of the
three nearest edge cells. This is an extremely powerful feature, as it provides logic cells
toward the center of the array with fast access to I/Os via local and express buses. It can
be seen from the diagram that a given Primary I/O can be accessed from any logic cell
on three separate rows or columns of the FPGA. See Figures 12a and 13a.
Secondary I/O
Every logic cell at the edge of the FPGA array has two direct diagonal connections to a
Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O
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