- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295111 > AT40KEL040KZ1SB (ATMEL CORP) FPGA, 2304 CLBS, 50000 GATES, PQFP256 PDF資料下載
參數(shù)資料
| 型號： | AT40KEL040KZ1SB |
| 廠商： | ATMEL CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2304 CLBS, 50000 GATES, PQFP256 |
| 封裝： | MQFP-256 |
| 文件頁數(shù)： | 39/42頁 |
| 文件大?。?/td> | 670K |
| 代理商： | AT40KEL040KZ1SB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁
6
AT40KEL040
4155G–AERO–05/05
The Busing Network
Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus
resources: a local-bus resource (the middle bus) and two express-bus (both sides)
resources. Bus resources are connected via repeaters. Each repeater has connections
to two adjacent local-bus segments and two express-bus segments. Each local-bus
segment spans four cells and connects to consecutive repeaters. Each express-bus
segment spans eight cells and “l(fā)eapfrogs” or bypasses a repeater. Repeaters regener-
ate signals and can connect any bus to any other bus (all pathways are legal) on the
same plane. Although not shown, a local bus can bypass a repeater via a programma-
ble pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are
implemented through pass gates in the cell-bus interface (see following page).
Express/Express turns are implemented through separate pass gates distributed
throughout the array.
Some of the bus resource on the AT40KEL040 is used as a dual-function resource.
Table 2 shows which buses are used in a dual-function mode and which bus plane is
used. The AT40KEL040 software tools are designed to accommodate dual-function
buses in an efficient manner.
Table 2. Dual-function Buses
Function
Type
Plane(s)
Direction
Comments
Cell Output Enable
Local
5
Horizontal and
Vertical
RAM Output Enable
Express
2
Vertical
Bus full length at array edge
Bus in first column to left of RAM block
RAM Write Enable
Express
1
Vertical
Bus full length at array edge
Bus in first column to left of RAM block
RAM Address
Express
1 - 5
Vertical
Buses full length at array edge
Buses in second column to left of RAM block
RAM Data In
Local
1
Horizontal
RAM Data Out
Local
2
Horizontal
Clocking
Express
4
Vertical
Bus half length at array edge
Set/Reset
Express
5
Vertical
Bus half length at array edge
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT89C2051-12SCT/R | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PDSO20 |
| AT89C51-24JCT/R | 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQCC44 |
| AT89C55-12JA | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQCC44 |
| AT90-1263TR | 0 MHz - 3000 MHz RF/MICROWAVE VARIABLE ATTENUATOR, 3.8 dB INSERTION LOSS-MAX |
| AT90S1200A-4YI | 8-BIT, FLASH, 4 MHz, RISC MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT40K-FFT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AT40K-FFT [Updated 8/98. 8 Pages] Fast fourier transform Intellectual Property Core for AT40K FPGAs |
| AT40KFL040 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad Hard Reprogrammable FPGAs with FreeRAM |
| AT40KFL040KW1-E | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad Hard Reprogrammable FPGAs with FreeRAM |
| AT40KFL040KW1-SCC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad Hard Reprogrammable FPGAs with FreeRAM |
| AT40KFL040KZ1-E | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Rad Hard Reprogrammable FPGAs with FreeRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。