參數(shù)資料
型號(hào)： AT40KEL040KZ1SB
廠商： ATMEL CORP
元件分類： FPGA
英文描述： FPGA, 2304 CLBS, 50000 GATES, PQFP256
封裝： MQFP-256
文件頁(yè)數(shù)： 4/42頁(yè)
文件大?。?/td> 670K
代理商： AT40KEL040KZ1SB
12
AT40KEL040
4155G–AERO–05/05
data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or
WE is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled
together; they both select CLOCK (for a synchronous RAM) or they both select “1” (for
an asynchronous RAM). CLOCK is obtained from the clock for the sector-column imme-
diately to the left and immediately above the RAM block. Writing any value to the RAM
clear byte during configuration clears the RAM (see the “AT40K/40KAL Configuration
Series” application note at www.atmel.com).
Figure 8. RAM Logic
Figure 9 on page 13 shows an exa mple of a RAM macro constructed u sing
AT40KEL040’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchro-
nous RAM. Note the very small amount of external logic required to complete the
address decoding for the macro. Most of the logic cells (core cells) in the sectors occu-
pied by the RAM will be unused: they can be used for other logic in the design. This
logic can be automatically generated using the macro generators.
Write Address
Din
Dout
Read Address
“1”
Write Enable NOT
RAM-Clear Byte
Dout
01
0
1
“1”
CLOCK
Load
5
Ain
Aout
WEN
Din
Load
Latch
Load
Latch
Load
Latch
Clear
32 x 4
Dual-port
RAM
OE
4
5
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