參數(shù)資料
型號(hào): AT80251G2D-SLSUL
廠商: Atmel
文件頁(yè)數(shù): 44/77頁(yè)
文件大小: 0K
描述: IC 8051 MCU ROMLESS 44PLCC
標(biāo)準(zhǔn)包裝: 972
系列: 8x251
核心處理器: C251
芯體尺寸: 8/16-位
速度: 16MHz
連通性: EBI/EMI,I²C,Microwire,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
49
AT/TSC8x251G2D
4135F–8051–11/06
Figure 10.
External Bus Cycle: Data Write (Non-Page Mode)
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
Waveforms in Page Mode
Figure 11.
External Bus Cycle: Code Fetch (Page Mode)
Note:
1. The value of this parameter depends on wait states. See Table 39 and Table 40.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch)
requires one state (2TOSC);
a page miss requires two states (4TOSC).
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit
cycle.
T
WHLH
TAVWL2
(1)
TAVWL1
(1)
TLHAX
(1)
TLLAX
TWHQX
TWHAX
P2/A16/A17
P0
WR#
ALE
TLHLL(1)
TWLWH(1)
Data Out
A15:8/A16/A17
TAVLL(1)
TQVWH
A7:0
D7:0
TLLAX
TAVDV2
(1)
TAVDV1(1)
TLHAX(1)
TAVRL(1)
TRHDZ1
TRLAZ
TAXDX
TAVDV3(1)
P0/A16/A17
P2
PSEN#(3)
ALE
TLHLL(1)
A7:0/A16/A17
TAVLL(1)
TLLRL(1)
TRLDV(1)
Page Miss(2)
Page Hit(2)
TRHAX
A7:0/A16/A17
D7:0
A15:8
Instruction In
TRHDX
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