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參數(shù)資料
| 型號： | AT80C51-25R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 169/170頁 |
| 文件大?。?/td> | 4133K |
| 代理商： | AT80C51-25R |
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ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Figure 14-6. Data changing and Data sampling.
The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the layer is in Receive
mode, waiting for a start bit. The mode of operation is controlled by the access layer.
14.3.7
Serial Data Reception
When the TPI physical layer is in receive mode, data reception is started as soon as a start bit has been detected.
Each bit that follows the start bit will be sampled at the rising edge of the TPICLK and shifted into the shift register
until the second stop bit has been received. When the complete frame is present in the shift register the received
data will be available for the TPI access layer.
There are three possible exceptions in the receive mode: frame error, parity error and break detection. All these
exceptions are signalized to the TPI access layer, which then enters the error state and puts the TPI physical layer
into receive mode, waiting for a BREAK character.
Frame Error Exception. The frame error exception indicates the state of the stop bit. The frame error exception
is set if the stop bit was read as zero.
Parity Error Exception. The parity of the data bits is calculated during the frame reception. After the frame is
received completely, the result is compared with the parity bit of the frame. If the comparison fails the parity
error exception is signalized.
Break Detection Exception. The Break detection exception is given when a complete frame of all zeros has
been received.
14.3.8
Serial Data Transmission
When the TPI physical layer is ready to send a new frame it initiates data transmission by loading the shift register
with the data to be transmitted. When the shift register has been loaded with new data, the transmitter shifts one
complete frame out on the TPIDATA line at the transfer rate given by TPICLK.
If a collision is detected during transmission, the output driver is disabled. The TPI access layer enters the error
state and the TPI physical layer is put into receive mode, waiting for a BREAK character.
14.3.9
Collision Detection Exception
The TPI physical layer uses one bi-directional data line for both data reception and transmission. A possible drive
contention may occur, if the external programmer and the TPI physical layer drive the TPIDATA line simultane-
ously. In order to reduce the effect of the drive contention, a collision detection mechanism is supported. The
collision detection is based on the way the TPI physical layer drives the TPIDATA line.
The TPIDATA line is driven by a tri-state, push-pull driver with internal pull-up. The output driver is always enabled
when a logical zero is sent. When sending successive logical ones, the output is only driven actively during the first
clock cycle. After this, the output driver is automatically tri-stated and the TPIDATA line is kept high by the internal
pull-up. The output is re-enabled, when the next logical zero is sent.
TPIDATA
TPICLK
SAMPLE
SETUP
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AT80C51ID2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 MCUs |
| AT80C51ID2-RLTIL | 功能描述:IC MCU 8051 3V SPI 20MHZ 44-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:80C 標準包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設備:POR，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT80C51ID2-RLTIM | 功能描述:IC MCU 8051 5V SPI 20MHZ 44-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:80C 標準包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設備:POR，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
| AT80C51ID2-RLTUL | 功能描述:8位微控制器 -MCU C51ID2 ROMless ind 3V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| AT80C51ID2-RLTUM | 功能描述:8位微控制器 -MCU C51ID2 ROMless ind 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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