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參數(shù)資料
| 型號(hào)： | AT80C51-25R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 170/170頁(yè) |
| 文件大?。?/td> | 4133K |
| 代理商： | AT80C51-25R |
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ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
The collision detection is enabled in transmit mode, when the output driver has been disabled. The data line should
now be kept high by the internal pull-up and it is monitored to see, if it is driven low by the external programmer. If
the output is read low, a collision has been detected.
There are some potential pit-falls related to the way collision detection is performed. For example, collisions cannot
be detected when the TPI physical layer transmits a bit-stream of successive logical zeros, or bit-stream of alter-
nating logical ones and zeros. This is because the output driver is active all the time, preventing polling of the
TPIDATA line. However, within a single frame the two stop bits should always be transmitted as logical ones,
enabling collision detection at least once per frame (as long as the frame format is not violated regarding the stop
bits).
The TPI physical layer will cease transmission when it detects a collision on the TPIDATA line. The collision is sig-
nalized to the TPI access layer, which immediately changes the physical layer to receive mode and goes to the
error state. The TPI access layer can be recovered from the error state only by sending a BREAK character.
14.3.10
Direction Change
In order to ensure correct timing of the half-duplex operation, a simple guard time mechanism has been added to
the physical layer. When the TPI physical layer changes from receive to transmit mode, a configurable number of
additional IDLE bits are inserted before the start bit is transmitted. The minimum transition time between receive
and transmit mode is two IDLE bits. The total IDLE time is the specified guard time plus two IDLE bits.
The guard time is configured by dedicated bits in the TPIPCR register. The default guard time value after the phys-
ical layer is initialized is 128 bits.
The external programmer looses control of the TPIDATA line when the TPI target changes from receive mode to
transmit. The guard time feature relaxes this critical phase of the communication. When the external programmer
changes from receive mode to transmit, a minimum of one IDLE bit should be inserted before the start bit is
transmitted.
14.4
Access Layer of Tiny Programming Interface
The TPI access layer is responsible for handling the communication with the external programmer. The communi-
cation is based on message format, where each message comprises an instruction followed by one or more byte-
sized operands. The instruction is always sent by the external programmer but operands are sent either by the
external programmer or by the TPI access layer, depending on the type of instruction issued.
The TPI access layer controls the character transfer direction on the TPI physical layer. It also handles the recov-
ery from the error state after exception.
The Control and Status Space (CSS) of the Tiny Programming Interface is allocated for control and status registers
in the TPI access Layer. The CSS consist of registers directly involved in the operation of the TPI itself. These reg-
ister are accessible using the SLDCS and SSTCS instructions.
The access layer can also access the data space, either directly or indirectly using the Pointer Register (PR) as the
address pointer. The data space is accessible using the SLD, SST, SIN and SOUT instructions. The address
pointer can be stored in the Pointer Register using the SLDPR instruction.
14.4.1
Message format
Each message comprises an instruction followed by one or more byte operands. The instruction is always sent by
the external programmer. Depending on the instruction all the following operands are sent either by the external
programmer or by the TPI.
The messages can be categorized in two types based on the instruction, as follows:
Write messages. A write message is a request to write data. The write message is sent entirely by the external
programmer. This message type is used with the SSTCS, SST, STPR, SOUT and SKEY instructions.
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| AT80C51ID2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 MCUs |
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| AT80C51ID2-RLTIM | 功能描述:IC MCU 8051 5V SPI 20MHZ 44-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:80C 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
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