參數(shù)資料
型號(hào): AT80C51RD2-RLTUM
廠商: Atmel
文件頁數(shù): 28/81頁
文件大?。?/td> 0K
描述: IC 8051 MCU 5V SPI 20MHZ 44-VQFP
標(biāo)準(zhǔn)包裝: 800
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LQFP
包裝: 托盤
34
4113D–8051–01/09
AT80C51RD2
11. Serial I/O Port
The serial I/O port in the AT80C51RD2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as a Univer-
sal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and
3). Asynchronous transmission and reception can occur simultaneously and at different baud
rates
Serial I/O port includes the following enhancements:
Framing error detection
Automatic address recognition
11.1
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 11-
Figure 11-1. Framing Error Block diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (see Table
11-4) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently, received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (see Figure
Figure 11-2. UART Timings in Mode 1
RI
TI
RB8
TB8
RE N
SM 2
SM 1
SM 0/FE
IDL
PD
GF0
GF1
PO F
-
SM OD0
SM OD1
To UA RT fra min g e rro r co nt ro l
SM 0 to UA RT m o de con tro l (SM OD0 = 0 )
Se t FE bit if stop bit is 0 (fram ing erro r) (SM OD0 = 1)
SCO N (9 8h )
PCON (87 h)
1
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD
D7
D6
D5
D4
D3
D2
D1
D0
FE
SMOD0=1
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