參數(shù)資料
型號(hào): AT89C51ID2-SLRUM
廠商: Atmel
文件頁數(shù): 153/157頁
文件大小: 0K
描述: IC 8051 MCU 64K FLASH 44-PLCC
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標(biāo)準(zhǔn)包裝: 500
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AT89C51ID2-SLRUMDKR
95
AT89C51ID2
4289C–8051–11/05
Registers
Table 71. SSCON Register
SSCON - Synchronous Serial Control register (93h)
76
543
210
CR2
SSIE
STA
STO
SI
AA
CR1
CR0
Bit
Number
Bit
Mnemonic
Description
7CR2
Control Rate bit 2
6SSIE
Synchronous Serial Interface Enable bit
Clear to disable the TWI module.
Set to enable the TWI module.
5STA
Start flag
Set to send a START condition on the bus.
4ST0
Stop flag
Set to send a STOP condition on the bus.
3SI
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
2AA
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
1CR1
Control Rate bit 1
0CR0
Control Rate bit 0
Table 72. SSDAT (095h) - Syncrhonous Serial Data register (read/write)
SD7SD6
SD5SD4
SD3SD2
SD1
SD0
76
543
210
Bit
Number
Bit
Mnemonic
Description
7
SD7
Address bit 7 or Data bit 7.
6
SD6
Address bit 6 or Data bit 6.
5
SD5
Address bit 5 or Data bit 5.
4
SD4
Address bit 4 or Data bit 4.
3
SD3
Address bit 3 or Data bit 3.
2
SD2
Address bit 2 or Data bit 2.
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