參數(shù)資料
型號： AT89C51ID2-SLRUM
廠商： Atmel
文件頁數(shù)： 22/157頁
文件大?。?/td> 0K
描述： IC 8051 MCU 64K FLASH 44-PLCC
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 500
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 60MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 標準包裝
其它名稱： AT89C51ID2-SLRUMDKR
118
AT89C51ID2
4289C–8051–11/05
Table 89. Program Lock Bits
Note:
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: do not care
WARNING: Security level 2 and 3 should only be programmed after Flash and code
verification.
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the "software security bits" which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its inactive state and will erase the Flash memory. The part ref-
erence can always be read using Flash parallel programming modes.
Default Values
The default value of the HSB provides parts ready to be programmed with ISP:
BLJB: Programmed force ISP operation.
X2: Unprogrammed to force X1 mode (Standard Mode).
XRAM: Unprogrammed to valid XRAM
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Software Registers
Several registers are used, in factory and by parallel programmers. These values are
used by Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
Commands issued by the parallel memory programmer.
Commands issued by the ISP software.
Calls of API issued by the application software.
Several software registers described in Table 90.
Program Lock Bits
Protection description
Security
level
LB0
LB1
LB2
1
U
No program lock features enabled.
2P
U
MOVC instruction executed from external program memory is disabled
from fetching code bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the on chip code
memory is disabled.
ISP and software programming with API are still allowed.
Writing EEprom Data from external parallel programmer is disabled but
still allowed from internal code execution.
3X
P
U
Same as 2, also verify code memory through parallel programming
interface is disabled.
Writing And Reading EEPROM Data from external parallel programmer
is disabled but still allowed from internal code execution..
4
X
P
Same as 3, also external execution is disabled. (Default)
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