- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄12024 > AT89C51ID2-SLSUM (Atmel)IC 8051 MCU FLASH 64K 44PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | AT89C51ID2-SLSUM |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 142/157頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 8051 MCU FLASH 64K 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | MCU Product Line Introduction |
| 標(biāo)準(zhǔn)包裝： | 972 |
| 系列： | 89C |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 60MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 2K x 8 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
| 配用： | AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)當(dāng)前第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
85
AT89C51ID2
4289C–8051–11/05
its own slave address followed by the data direction bit which must be at logic 1 (R) for
TWI to operate in the slave transmitter mode. After its own slave address and the R bit
have been received, the serial interrupt flag is set and a valid status code can be read
from SSCS. This status code is used to vector to an interrupt service routine. The appro-
priate action to be taken for each of these status code is detailed in Table . The slave
transmitter mode may also be entered if arbitration is lost while the TWI module is in the
master mode.
If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the
transfer and enter state C0h or C8h. the TWI module is switched to the not addressed
slave mode and will ignore the master receiver if it continues the transfer. Thus the mas-
ter receiver receives all 1’s as serial data. While AA is reset, the TWI module does not
respond to its own slave address. However, the 2-wire bus is still monitored and
address recognition may be resume at any time by setting AA. This means that the AA
bit may be used to temporarily isolate the TWI module from the 2-wire bus.
Miscellaneous States
There are two SSCS codes that do not correspond to a define TWI hardware state
(Table 70 ). These codes are discuss hereafter.
Status F8h indicates that no relevant information is available because the serial interrupt
flag is not set yet. This occurs between other states and when the TWI module is not
involved in a serial transfer.
Status 00h indicates that a bus error has occurred during a TWI serial transfer. A bus
error is caused when a START or a STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions happen during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To
recover from a bus error, the STO flag must be set and SI must be cleared. This causes
the TWI module to enter the not addressed slave mode and to clear the STO flag (no
other bits in SSCON are affected). The SDA and SCL lines are released and no STOP
condition is transmitted.
Notes
the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock
line) and SDA (serial data line). To avoid low level asserting on these lines when the
TWI module is enabled, the output latches of SDA and SLC must be set to logic 1.
Table 65. Bit Frequency Configuration
Bit Frequency ( kHz)
CR2
CR1
CR0
F
OSCA= 12 MHz
F
OSCA = 16 MHz
F
OSCA divided by
0
47
62.5
256
0
1
53.5
71.5
224
0
1
0
62.5
83
192
0
1
75
100
160
1
0
-
Unused
1
0
1
100
133.3
120
1
0
200
266.6
60
1
0.5 <. < 62.5
0.67 <. < 83
96 (256 - reload valueTimer 1)
(reload value range: 0-254 in mode 2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT91SAM7X128B-CU | IC MCU 128KB FLASH 100TFBGA |
| AT91SAM7XC128B-AU | MCU ARM 128K HS FLASH 100-LQFP |
| ATSAM3U1CA-CU | IC MCU 32BIT 64KB FLASH 100TFBGA |
| 1981584-1 | CONN RCPT MICRO USB TYPE AB |
| 1981568-1 | CONN RCPT MICRO USB B R/A SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT89C51ID2-SMSIM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller |
| AT89C51ID2-UM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller |
| AT89C51RB2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16K/ 32K Bytes Flash |
| AT89C51RB2/RC2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:AT89C51RB2/RC2 [Updated 4/03. 125 Pages] |
| AT89C51RB2_06 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 16K/ 32K Bytes Flash |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。