參數(shù)資料
型號： AT89C51ID2-SLSUM
廠商： Atmel
文件頁數(shù)： 79/157頁
文件大小： 0K
描述： IC 8051 MCU FLASH 64K 44PLCC
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 972
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 60MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 2K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
配用： AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
28
AT89C51ID2
4289C–8051–11/05
Expanded RAM
(XRAM)
The AT89C51ID2 provides additional Bytes of random access memory (RAM) space for
increased data parameter handling and high level language usage.
AT89C51ID2 devices have expanded RAM in external data space configurable up to
1792bytes (see Table 24.).
The AT89C51ID2 has internal data memory that is mapped into four separate
segments.
The four segments are:
1.
The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2.
The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable
only.
3.
The Special Function Registers, SFRs, (addresses 80h to FFh) are directly
addressable only.
4.
The expanded RAM bytes are indirectly accessed by MOVX instructions, and
with the EXTRAM bit cleared in the AUXR register (see Table 24).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
Figure 6. Internal and External Data Memory Address
When an instruction accesses an internal location above address 7Fh, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0A0h (which is P2).
Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte
at address 0A0h, rather than P2 (whose address is 0A0h).
The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared
and MOVX instructions. This part of memory which is physically located on-chip,
logically occupies the first bytes of external data memory. The bits XRS0 and XRS1
are used to hide a part of the available XRAM as explained in Table 24. This can be
XRAM
Upper
128 bytes
Internal
Ram
Lower
128 bytes
Internal
Ram
Special
Function
Register
80h
00
0FFh to 6FFh
0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 06FFh
0FFFFh
indirect accesses
direct accesses
direct or indirect
accesses
7Fh
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