VDD = 2.7 to 3.3 V, TA " />
參數(shù)資料
型號: AT89C51SND1C-7HTUL
廠商: Atmel
文件頁數(shù): 27/42頁
文件大?。?/td> 0K
描述: IC MCU 64KB FLASH MEM 81-CBGA
標(biāo)準(zhǔn)包裝: 250
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 44
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-CBGA
包裝: 托盤
33
4109LS–8051–02/08
AT8xC51SND1C
VDD = 2.7 to 3.3 V, TA = -40 to +85°C
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this
must be < 1 s.
3. Spikes on the SDA and SCL lines with a duration of less than 3TCLCL will be filtered out. Maxi-
mum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= TOSC= one oscillator clock period.
7.4.1.2
Waveforms
Figure 7-18. Two Wire Waveforms
Symbol
Parameter
INPUT
Min
Max
OUTPUT
Min
Max
THD; STA
Start condition hold time
14TCLCL(4)
4.0 s(1)
TLOW
SCL low time
16TCLCL(4)
4.7 s(1)
THIGH
SCL high time
14TCLCL(4)
4.0 s(1)
TRC
SCL rise time
1 s
-(2)
TFC
SCL fall time
0.3 s
0.3 s(3)
TSU; DAT1
Data set-up time
250 ns
20TCLCL(4)- TRD
TSU; DAT2
SDA set-up time (before repeated START condition)
250 ns
1 s(1)
TSU; DAT3
SDA set-up time (before STOP condition)
250 ns
8TCLCL(4)
THD; DAT
Data hold time
0 ns
8TCLCL(4) - TFC
TSU; STA
Repeated START set-up time
14TCLCL(4)
4.7 s(1)
TSU; STO
STOP condition set-up time
14TCLCL(4)
4.0 s(1)
TBUF
Bus free time
14TCLCL(4)
4.7 s(1)
TRD
SDA rise time
1 s
-(2)
TFD
SDA fall time
0.3 s
0.3 s(3)
Tsu;DAT1
Tsu;STA
Tsu;DAT2
Thd;STA
T
high
Tlow
SDA
(INPUT/OUTPUT)
0.3 VDD
0.7 V
DD
T
buf
T
su;STO
0.7 V
DD
0.3 V
DD
Trd
T
fd
T
rc
T
fc
SCL
(INPUT/OUTPUT)
T
hd;DAT
Tsu;DAT3
START or Repeated START condition
START condition
STOP condition
Repeated START condition
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