參數(shù)資料
型號: AT89C51SND1C-7HTUL
廠商: Atmel
文件頁數(shù): 40/42頁
文件大小: 0K
描述: IC MCU 64KB FLASH MEM 81-CBGA
標(biāo)準(zhǔn)包裝: 250
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 44
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 81-CBGA
包裝: 托盤
7
4109LS–8051–02/08
AT8xC51SND1C
Table 4. Audio Interface Signal Description
Table 5. USB Controller Signal Description
Table 6. MutiMediaCard Interface Signal Description
T0
I
Timer 0 External Clock Input
When timer 0 operates as a counter, a falling edge on the T0 pin
increments the count.
P3.4
T1
I
Timer 1 External Clock Input
When timer 1 operates as a counter, a falling edge on the T1 pin
increments the count.
P3.5
Signal
Name
Type
Description
Alternate
Function
DCLK
O
DAC Data Bit Clock
-
DOUT
O
DAC Audio Data
-
DSEL
O
DAC Channel Select Signal
DSEL is the sample rate clock output.
-
SCLK
O
DAC System Clock
SCLK is the oversampling clock synchronized to the digital audio data
(DOUT) and the channel selection signal (DSEL).
-
Signal
Name
Type
Description
Alternate
Function
D+
I/O
USB Positive Data Upstream Port
This pin requires an external 1.5 K pull-up to VDD for full speed
operation.
-
D-
I/O
USB Negative Data Upstream Port
-
Signal
Name
Type
Description
Alternate
Function
MCLK
O
MMC Clock output
Data or command clock transfer.
-
MCMD
I/O
MMC Command line
Bidirectional command channel used for card initialization and data
transfer commands. To avoid any parasitic current consumption,
unused MCMD input must be polarized to VDD or VSS.
-
MDAT
I/O
MMC Data line
Bidirectional data channel. To avoid any parasitic current consumption,
unused MDAT input must be polarized to VDD or VSS.
-
Signal
Name
Type
Description
Alternate
Function
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