參數(shù)資料
型號: AT89LP4052-16PU
廠商: Atmel
文件頁數(shù): 20/94頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 4K 20DIP
標(biāo)準(zhǔn)包裝: 18
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 16MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
27
3547J–MICRO–10/09
AT89LP2052/LP4052
Table 16-1.
TCON
– Timer/Counter Control Register
TCON = 88H
Reset Value = 0000 0000B
Bit Addressable
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
7
65
43
21
0
Symbol
Function
TF1
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to
interrupt routine.
TR1
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.
TF0
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to
interrupt routine.
TR0
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.
IE1
Interrupt 1 flag. When IT1 is set, IE1 is set by hardware when the external interrupt falling edge is detected, and is cleared
by hardware when the CPU vectors to the interrupt routine. When IT1 is cleared, IE1 is sampled and inverted from the
external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.3.
IT1
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
IE0
Interrupt 0 flag. When IT0 is set, IE0 is set by hardware when the external interrupt falling edge is detected, and is cleared
by hardware when the CPU vectors to the interrupt routine. When IT0 is cleared, IE0 is sampled and inverted from the
external interrupt pin. The flag will be set or cleared by hardware depending on the state of P3.2.
IT0
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
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