參數(shù)資料
型號(hào): AT89LP4052-16XU
廠商: Atmel
文件頁(yè)數(shù): 15/94頁(yè)
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 4K 20TSSOP
標(biāo)準(zhǔn)包裝: 74
系列: 89LP
核心處理器: 8051
芯體尺寸: 8-位
速度: 16MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
包裝: 管件
22
3547J–MICRO–10/09
AT89LP2052/LP4052
15.3
Open-drain Output
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port register contains a logic “0”. To be used as a logic output, a port
configured in this manner must have an external pull-up, typically a resistor tied to V
CC. The pull-
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in Figure 15-4. The input circuitry of P3.2 and P3.3 is not disabled during Power-
down (see Figure 15-3).
Figure 15-4. Open-Drain Output
15.4
Push-pull Output
The push-pull output configuration has the same pull-down structure as both the open-drain and
the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port
register contains a logic “1”. The push-pull mode may be used when more source current is
needed from a port output. The push-pull port configuration is shown in Figure 15-5. The input
circuitry of P3.2 and P3.3 is not disabled during Power-down (see Figure 15-3).
Figure 15-5. Push-pull Output
15.5
Port 1 Analog Functions
The AT89LP2052/LP4052 incorporates an analog comparator. In order to give the best analog
performance and minimize power consumption, pins that are being used for analog functions
must have both the digital outputs and digital inputs disabled. Digital outputs are disabled by put-
ting the port pins into the input-only mode as described in Section 15. “I/O Ports” on page 20.
Digital inputs on P1.0 and P1.1 are disabled whenever the Analog Comparator is enabled by
setting the CEN bit in ACSR. CEN forces the PWD input on P1.0 and P1.1 low, thereby disabling
the Schmitt trigger circuitry.
Port
Pin
From Port
Register
Input
Data
PWD
Port
Pin
VCC
From Port
Register
Input
Data
PWD
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