參數(shù)資料
型號(hào)： AT89LP4052-20PU
廠商： Atmel
文件頁(yè)數(shù)： 7/94頁(yè)
文件大小： 0K
描述： IC 8051 MCU FLASH 4K 20DIP
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 18
系列： 89LP
核心處理器： 8051
芯體尺寸： 8-位
速度： 20MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 15
程序存儲(chǔ)器容量： 4KB（4K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 616 (CN2011-ZH PDF)
15
3547J–MICRO–10/09
AT89LP2052/LP4052
13.1
Idle Mode
Setting the IDL bit in PCON enters Idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. The Timer, UART and SPI blocks continue to function dur-
ing Idle. The comparator and watchdog may be selectively enabled or disabled during Idle. Any
enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an inter-
rupt, the interrupt will immediately be serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put the device into Idle.
13.2
Power-down Mode
Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops
the oscillator and powers down the Flash memory in order to minimize power consumption. Only
the power-on circuitry will continue to draw power during Power-down. During Power-down, the
power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be
retained, but the SFR contents are not guaranteed once V
CC has been reduced. Power-down
may be exited by external reset, power-on reset, or certain interrupts.
The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 s
until after one of the following conditions has occurred: Start of code execution (after any type of
reset), or Exit from power-down mode.
13.2.1
Interrupt Recovery from Power-down
Two external interrupts may be configured to terminate Power-down mode. Pins P3.2 and P3.3
may be used to exit Power-down through external interrupts INT0 and INT1. To wake up by
external interrupts INT0 or INT1, that interrupt must be enabled and configured for level-sensi-
tive operation. If configured as inputs, INT0 and INT1 should not be left floating during Power-
down even if interrupt recovery is not used.
When terminating Power-down by an interrupt, two different wake-up modes are available.
When PWDEX in PCON is zero, the wake-up period is internally timed. At the falling edge on the
interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins count-
ing. The internal clock will not be allowed to propagate to the CPU until after the timer has
counted for nominally 2 ms. After the time-out period the interrupt service routine will begin. The
interrupt pin may be held low until the device has timed out and begun executing, or it may
return high before the end of the time-out period. If the pin remains low, the service routine
should disable the interrupt before returning to avoid re-triggering the interrupt.
When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, Power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin. The interrupt should
be held low long enough for the selected clock source to stabilize.
13.2.2
Reset Exit from Power-down
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU
until after the timer has counted for nominally 2 ms. The RST pin must be held high for longer
than the time-out period to ensure that the device is reset properly. The device will begin execut-
ing once RST is brought back low.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT89LP4052-20SU 功能描述:8位微控制器 -MCU SINGLE CYCLE 4K FLASH-20MHZ 2.4-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP4052-20XU 功能描述:8位微控制器 -MCU SINGLE CYC 4K FLASH -20MHZ 2.4-5.5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP4052W-10SU 功能描述:8位微控制器 -MCU SINGLE CYCLE 4K ISP FLASH 2.0-3.6V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP4052W-10XU 功能描述:8位微控制器 -MCU SINGLE CYCLE 4K ISP FLASH 2.0-3.6V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP428-20AU 功能描述:8位微控制器 -MCU SingleCycle 8051 4K ISP Flash 2.4V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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