參數(shù)資料
型號： AT89LP428-20MH
廠商： Atmel
文件頁數(shù)： 24/149頁
文件大?。?/td> 0K
描述： MCU 8051 4K FLASH SPI 32VQFN
產(chǎn)品培訓(xùn)模塊： MCU Product Line Introduction
標(biāo)準(zhǔn)包裝： 490
系列： 89LP
核心處理器： 8051
芯體尺寸： 8-位
速度： 20MHz
連通性： SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 30
程序存儲器容量： 4KB（4K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.4 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VFQFN 裸露焊盤
包裝： 托盤
12
3654A–MICRO–8/09
AT89LP428/828
3.3.2
FDATA
The Flash data memory is a portion of the external memory space implemented as an internal
nonvolatile data memory. Flash data memory is enabled by setting the DMEN bit (MEMCON.3)
to one. When IAP = 0 and DMEN = 1, the Flash data memory is mapped into the FDATA space,
directly above the EDATA space near the bottom of the external memory address space.
(Addresses 0200H–03FFH on AT89LP428 and 0200H–05FFH on AT89LP828. See Figure 3-3
on page 11). MOVX instructions to this address range will access the internal nonvolatile mem-
ory. FDATA is not accessible while DMEN = 0. FDATA can be accessed only by 16-bit
(MOVX @DPTR) addresses. Addresses above the FDATA range are not implemented and
should not be accessed. MOVX instructions to FDATA require a minimum of 4 clock cycles.
3.3.2.1
Write Protocol
The FDATA address space accesses an internal nonvolatile data memory. This address space
can be read just like EDATA by issuing a MOVX A,@DPTR; however, writes to FDATA require a
more complex protocol and take several milliseconds to complete. The AT89LP428/828 uses an
idle-while-write architecture where the CPU is placed in an idle state while the write occurs.
When the write completes, the CPU will continue executing with the instruction after the
MOVX @DPTR,A instruction that started the write. All peripherals will continue to function during
the write cycle; however, interrupts will not be serviced until the write completes.
To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be set
to one. When MWEN = 1 and DMEN = 1, MOVX @DPTR,A may be used to write to FDATA.
FDATA uses Flash memory with a page-based programming model. Flash data memory differs
from traditional EEPROM data memory in the method of writing data. EEPROM generally can
update a single byte with any value. Flash memory splits programming into write and erase
operations. A Flash write can only program zeroes, i.e change ones into zeroes (). Any
ones in the write data are ignored. A Flash erase sets an entire page of data to ones so that all
bytes become FFH. Therefore after an erase, each byte in the page can be written once with
any possible value. Bytes can be overwritten without an erase as long as only ones are changed
into zeroes. However, if even a single bit needs updating from zero to one (
); then the con-
tents of the page must first be saved, the entire page must be erased and the zero bits in all
bytes (old and new data combined) must be written. Avoiding unnecessary page erases greatly
improves the endurance of the memory.
The AT89LP428/828 includes 8/16 data pages of 64 bytes each. One or more bytes in a page
may be written at one time. The AT89LP428/828 includes a temporary page buffer of 64 bytes,
so the maximum number of bytes written at one time is 64. The LDPG bit (MEMCON.5) allows
m u ltiple d a ta b yte s to b e lo a d ed to the tempor a ry p a ge bu ffer. While LDPG = 1 ,
MOVX @DPTR,A instructions will load data to the page buffer, but will not start a write
sequence. Note that a previously loaded byte must not be reloaded prior to the write sequence.
To write the page into the memory, LDPG must first be cleared and then a MOVX @DPTR,A
with the final data byte is issued. The address of the final MOVX determines which page will be
written. If a MOVX @DPTR,A instruction is issued while LDPG = 0 without loading any previous
bytes, only a single byte will be written. The page buffer is reset after each write operation. Fig-
ures 3-4 and 3-5 show the difference between byte writes and page writes.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT89LP428-20PU 功能描述:8位微控制器 -MCU SingleCycle 8051 4K ISP Flash 2.4V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP51-20AU 功能描述:8位微控制器 -MCU Single Cycle 8051 4K ISP FL RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP51-20JU 功能描述:8位微控制器 -MCU Single Cycle 8051 4K ISP FL RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP51-20MU 功能描述:8位微控制器 -MCU Single Cycle 8051 4K ISP FL RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89LP51-20PU 功能描述:8位微控制器 -MCU Single Cycle 8051 4K ISP FL RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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