參數(shù)資料
型號: AT89S8253-24AU
廠商: Atmel
文件頁數(shù): 34/60頁
文件大?。?/td> 0K
描述: IC MCU 12K FLASH 24MHZ 44-TQFP
產(chǎn)品培訓(xùn)模塊: MCU Product Line Introduction
標準包裝: 160
系列: 89S
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 616 (CN2011-ZH PDF)
4
3286P–MICRO–3/10
AT89S8253
3.5
PWRGND
Ground for the 42-PDIP which connects only the I/O Pad Drivers. PWRGND and GND are
weakly connected through the common silicon substrate, but not through any metal links. The
application board must connect both GND and PWRGND to the board ground.
3.6
Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink six TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-
ing program verification. External pull-ups are required during program verification.
3.7
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source six TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the weak
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (I
IL,150 A typical) because of the weak internal pull-ups.
Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX),
respectively. Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port
select, data input/output and shift clock input/output pins as shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and verification.
3.8
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source six TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the weak
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (I
IL,150 A typical) because of the weak internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and dur-
ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2
Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash
programming and verification.
Port Pin
Alternate Functions
P1.0
T2 (external count input to Timer/Counter 2), clock-out
P1.1
T2EX (Timer/Counter 2 capture/reload trigger and direction control)
P1.4
SS (Slave port select input)
P1.5
MOSI (Master data output, slave data input pin for SPI channel)
P1.6
MISO (Master data input, slave data output pin for SPI channel)
P1.7
SCK (Master clock output, slave clock input pin for SPI channel)
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