參數(shù)資料
型號: AT89S8253-24PC
廠商: Atmel
文件頁數(shù): 13/60頁
文件大小: 0K
描述: IC 8051 MCU FLASH 12K 40DIP
標(biāo)準(zhǔn)包裝: 10
系列: 89S
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
20
3286P–MICRO–3/10
AT89S8253
13. UART
The UART in the AT89S8253 operates the same way as the UART in the AT89S51 and
AT89S52. For more detailed information on the UART operation, please click on the document
link below:
13.1
Enhanced UART
In addition to all of its usual modes, the UART can perform framing error detection by looking for
missing stop bits, and automatic address recognition. The UART also fully supports multiproces-
sor communication as does the standard 80C51 UART.
When used for framing error detect, the UART looks for missing stop bits in the communication.
A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0
and the function of SCON.7 is determined by PCON.6 (SMOD0). If SMOD0 is set then SCON.7
functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE,
SCON.7 can only be cleared by software.
13.1.1
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART to recognize certain
addresses in the serial bit stream by using hardware to make the comparisons. This feature
saves a great deal of software overhead by eliminating the need for the software to examine
every serial address which passes by the serial port. This feature is enabled by setting the SM2
bit in SCON. In the 9-bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will
be automatically set when the received byte contains either the “Given” address or the
“Broadcast” address. The 9-bit mode requires that the 9th information bit is a 1 to indicate that
the received information is an address and not data.
The 8-bit mode is called mode 1. In this mode the RI flag will be set if SM2 is enabled and the
information received has a valid stop bit following the 8 address bits and the information is either
a Given or Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to selectively communicate
with one or more slaves by invoking the given slave address or addresses. All of the slaves may
be contacted by using the Broadcast address. Two special Function Registers are used to
define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define
which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can
be logically ANDed with the SADDR to create the “Given” address which the master will use for
addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the versatility of this scheme:
Slave 0
SADDR = 1100 0000
SADEN = 1111 1101
Given
= 1100 00X0
Slave 1
SADDR = 1100 0000
SADEN = 1111 1110
Given
= 1100 000X
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