參數(shù)資料
型號(hào)： AT89S8253-24PC
廠(chǎng)商： Atmel
文件頁(yè)數(shù)： 7/60頁(yè)
文件大小： 0K
描述： IC 8051 MCU FLASH 12K 40DIP
標(biāo)準(zhǔn)包裝： 10
系列： 89S
核心處理器： 8051
芯體尺寸： 8-位
速度： 24MHz
連通性： SPI，UART/USART
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 12KB（12K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大小： 2K x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
15
3286P–MICRO–3/10
AT89S8253
10.1
Timer 2 Registers
Control and status bits are contained in registers T2CON (see Table 10-2) and T2MOD (see
Table 10-3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers
for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
10.2
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is
a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used
to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-
tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into
RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus-
trated in Figure 10-1.
Table 10-2.
T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H
Reset Value = 0000 0000B
Bit Addressable
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Bit
7
654
321
0
Symbol
Function
TF2
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
EXF2
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
TCLK
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
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