osc = oscillator frequency. 14" />
參數(shù)資料
型號: AT89S8253-24PC
廠商: Atmel
文件頁數(shù): 16/60頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 12K 40DIP
標準包裝: 10
系列: 89S
核心處理器: 8051
芯體尺寸: 8-位
速度: 24MHz
連通性: SPI,UART/USART
外圍設備: POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
EEPROM 大小: 2K x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
23
3286P–MICRO–3/10
AT89S8253
Notes:
1. SMOD0 is located at PCON.6.
2. f
osc = oscillator frequency.
14. Serial Peripheral Interface
The serial peripheral interface (SPI) allows high-speed synchronous data transfer between the
AT89S8253 and peripheral devices or between multiple AT89S8253 devices. The AT89S8253
SPI features include the following:
Full-Duplex, 3-Wire Synchronous Data Transfer
Master or Slave Operation
Maximum Bit Frequency = f/4 (f/2 if in x2 Clock Mode)
LSB First or MSB First Data Transfer
Four Programmable Bit Rates in Master Mode
End of Transmission Interrupt Flag
Write Collision Flag Protection
Double-Buffered Receive
Double-Buffered Transmit (Enhanced Mode only)
Wakeup from Idle Mode (Slave Mode only)
The interconnection between master and slave CPUs with SPI is shown in Figure 14-1. The four
pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock
(SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is the clock
input in slave mode. The MSTR bit in SPCR determines the directions of MISO and MOSI. Also
notice that MOSI connects to MOSI and MISO to MISO. In master mode, SS/P1.4 is ignored and
may be used as a general-purpose input or output. In slave mode, SS must be driven low to
select an individual device as a slave. When SS is driven high, the slave’s SPI port is deacti-
vated and the MOSI/P1.5 pin can be used as a general-purpose input.
Figure 14-1. SPI Master-Slave Interconnection
8-BIT SHIFT REGISTER
MASTER
CLOCK GENERATOR
SPI
MISO
8-BIT SHIFT REGISTER
SLAVE
MISO
MOSI MOSI
SCK
SS
V
CC
MSB
LSB
MSB
LSB
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