參數(shù)資料
型號: AT90S4433-8AC
廠商: Atmel
文件頁數(shù): 75/126頁
文件大?。?/td> 0K
描述: IC MCU 4K FLSH 8MHZ A/D 32TQFP
標準包裝: 250
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 32-TQFP
包裝: 托盤
52
AT90S/LS4433
1042H–AVR–04/03
SPI Status Register – SPSR
Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then by accessing the SPI Data Register (SPDR).
Bit 6 – WCOL: Write Collision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Reg-
ister with WCOL set (one), and then by accessing the SPI Data Register.
Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and will always read as zero.
The SPI interface on the AT90S4433 is also used for Program memory and EEPROM
downloading or uploading. See page 93 for Serial Programming and verification.
SPI Data Register – SPDR
The SPI Data Register is a read/write register used for data transfer between the Regis-
ter File and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Bit
7654
321
0
$0E ($2E)
SPIF
WCOL
SPSR
Read/Write
R
RRRR
RRR
Initial Value
0000
000
0
Bit
7654
321
0
$0F ($2F)
MSB
LSB
SPDR
Read/Write
R/W
Initial Value
X
Undefined
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