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參數(shù)資料
| 型號： | AT91M42800A-33CJ-999 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 5/27頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT RISC 144BGA |
| 標準包裝： | 1 |
| 系列： | AT91 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設備： | POR，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LFBGA |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | AT91M42800A-33CJ-999CT |
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13
1779ES–ATARM–14-Apr-06
AT91M42800A
Figure 7-1.
Seperate or Common Reset Management
Notes:
1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
In order to benefit from the separation of NRST and NTRST during the debug phase of develop-
ment, the user must independently manage both signals as shown in example (1) of Figure 7-1
above. However, once debug is completed, both signals are easily managed together during
production as shown in example (2) of Figure 7-1 above.
7.5.3
Watchdog Reset
The internally generated watchdog reset has the same effect as the NRST pin, except that the
pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. The
NRST pin has priority if both types of reset coincide.
7.6
Emulation Functions
7.6.1
Tri-state Mode
The AT91M42800A provides a Tri-state mode, which is used for debug purposes in order to
connect an emulator probe to an application board. In Tri-state mode the AT91M42800A contin-
ues to function, but all the output pin drivers are tri-stated.
To enter Tri-state mode, the pin NTRI must be held low during the last 10 SLCK clock cycles
before the rising edge of NRST. For normal operation, the pin NTRI must be held high during
reset, by a resistor of up to 400 k
. NTRI must be driven to a valid logic value during reset.
NTRI is multiplexed with Parallel I/O PA9 and USART 1 serial data transmit line TXD1.
Standard RS232 drivers generally contain internal 400 k
pull-up resistors. If TXD1 is connected
to one of these drivers, this pull-up will ensure normal operation, without the need for an addi-
tional external resistor.
7.6.2
Embedded ICE
ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. It is con-
nected to a host computer via an embedded ICE Interface.
Embedded ICE mode is selected when MODE1 is low.
It is not possible to switch directly between ICE and JTAG operations. A chip reset must be per-
formed (NRST and NTRST) after MODE0 and/or MODE1 have/has been changed. The reset
input to the Embedded ICE (NTRST) is provided separately to facilitate debug of boot programs.
(1)
(2)
Reset
Controller
Reset
Controller
Reset
Controller
NTRST
NRST
NTRST
NRST
AT91M42800A
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