參數(shù)資料
型號(hào)： AT91M42800A-33CJ-999
廠商： Atmel
文件頁(yè)數(shù)： 9/27頁(yè)
文件大?。?/td> 0K
描述： IC MCU 32BIT RISC 144BGA
標(biāo)準(zhǔn)包裝： 1
系列： AT91
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 33MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 54
程序存儲(chǔ)器類型： ROMless
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LFBGA
包裝： 剪切帶 (CT)
其它名稱： AT91M42800A-33CJ-999CT
17
1779ES–ATARM–14-Apr-06
AT91M42800A
8.3
Peripheral Data Controller
The AT91M42800A has an 8-channel PDC dedicated to the two on-chip USARTs and to the two
on-chip SPIs. One PDC channel is connected to the receiving channel and one to the transmit-
ting channel of each peripheral.
The user interface of a PDC channel is integrated in the memory space of each USART channel
and in the memory space of each SPI. It contains a 32-bit address pointer register and a 16-bit
count register. When the programmed data is transferred, an end-of-transfer interrupt is gener-
ated by the corresponding peripheral. See the USART section and the SPI sections for more
details on PDC operation and programming.
8.4
System Peripherals
8.4.1
PMC: Power Management Controller
The AT91M42800A’s Power Management Controller optimizes the power consumption of the
device. The PMC controls the clocking elements such as the oscillator and the PLLs, and the
System and the Peripheral Clocks. It also controls the MCKO pin and permits to the user to
select four different signals to be driven on this pin.
The AT91M42800A has the following clock elements:
The oscillator providing a clock that depends on the crystal fundamental frequency
connected between the XIN and XOUT pins
PLL A providing a low-to-middle frequency clock range
PLL B providing a middle-to-high frequency range
The Clock prescaler
The ARM Processor Clock controller
The Peripheral Clock controller
The Master Clock Output controller
The on-chip low-power oscillator together with the PLL-based frequency multiplier and the pres-
caler results in a programmable clock between 500 Hz and 66 MHz. It is the responsibility of the
user to make sure that the PMC programming does not result in a clock over the acceptable
limits.
8.4.2
ST: System Timer
The System Timer module integrates three different free-running timers:
A Period Interval Timer setting the base time for an Operating System.
A Watchdog Timer that is built around a 16-bit counter, and is used to prevent system lock-up
if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt,
or assert an active level on the dedicated pin NWDOVF.
A Real-time Timer counting elapsed seconds.
These timers count using the Slow Clock provided by the MCU. Typically, this clock has a fre-
quency of 32768 Hz.
8.4.3
AIC: Advanced Interrupt Controller
The AT91M42800A has an 8-level priority, individually maskable, vectored interrupt controller.
This feature substantially reduces the software and real-time overhead in handling internal and
external interrupts.
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