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參數(shù)資料
| 型號： | ATF1508AS-10QI160 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 30/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 10NS 160PQFP |
| 標準包裝： | 24 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508AS10QI160 |
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8
ATF1508AS(L)
0784P–PLD–7/05
Design
Software
Support
ATF1508AS designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high level description languages and formats.
Power-up Reset
The ATF1508AS is designed with a power-up reset, a feature critical for state machine initial-
ization. At a point delayed slightly from V
CC crossing VRST, all registers will be initialized, and
the state of each output will depend on the polarity of its buffer. However, due to the asynchro-
nous nature of reset and uncertainty of how V
CC actually rises in the system, the following
conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and,
3.
The clock must remain stable during T
D.
The ATF1508AS has two options for the hysteresis about the reset level, V
RST, Small and
Large. During the fitting process users may configure the device with the Power-up Reset hys-
teresis set to Large or Small. Atmel POF2JED users may select the Large option by including
the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be
properly reinitialized with the Large hysteresis option selected, the following condition is
added:
4.
If V
CC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, I
CC is reduced by several hundred microamps as
well.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of the ATF1508AS fuse patterns.
Once programmed, fuse verify is inhibited. However, User Signature and device ID remains
accessible.
Programming
ATF1508AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG pro-
tocol. This capability eliminates package handling normally required for programming and
facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1508AS via the
PC. ISP is performed by using either a download cable or a comparable board tester or a sim-
ple microprocessor interface.
To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial
Vector Format (SVF) files can be created by the Atmel ISP Software. Conversion to other ATE
tester format beside SVF is also possible
ATF1508AS devices can also be programmed using standard third-party programmers. With
third-party programmer, the JTAG ISP port can be disabled thereby allowing four additional
I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1508AS-10QL100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF1508AS-10QL160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF1508AS-10QU100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 10NS IND TEMP GRN RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-15AC100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 5V ISP CPLD 100 PIN 15NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-15AI100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MC CPLD 15NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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