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參數(shù)資料
| 型號： | ATF1508AS-10QI160 |
| 廠商： | Atmel |
| 文件頁數(shù)： | 5/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 10NS 160PQFP |
| 標準包裝： | 24 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應商設備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | ATF1508AS10QI160 |
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13
ATF1508AS(L)
0784P–PLD–7/05
Power-down
Mode
The ATF1508AS includes two pins for optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high,
the device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched and held. Therefore, all registered and combinatorial out-
put data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-
Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O
hold latches remain active to ensure that pins do not float to indeterminate levels, further
reducing system power. The power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD pin logic array input. However, bur-
ied logic resources in this macrocell may still be used.
Notes:
1. For slow slew outputs, add tSSO.
2. Pin or product term.
Power-down AC Characteristics(1)(2)
Symbol
Parameter
-7
-10
-15
-20
-25
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tIVDH
Valid I, I/O before PD High
7
10
15
20
25
ns
t
GVDH
Valid OE(2) before PD High
7
10
15
20
25
ns
t
CVDH
Valid Clock(2) before PD High
7
10
15
20
25
ns
tDHIX
I, I/O Don’t Care after PD High
12
15
25
30
35
ns
t
DHGX
OE(2) Don’t Care after PD High
12
15
25
30
35
ns
t
DHCX
Clock(2) Don’t Care after PD High
1215253035
ns
tDLIV
PD Low to Valid I, I/O
1
s
t
DLGV
PD Low to Valid OE (Pin or Term)
1
s
t
DLCV
PD Low to Valid Clock (Pin or Term)
1
s
tDLOV
PD Low to Valid Output
1
s
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1508AS-10QL100 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF1508AS-10QL160 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF1508AS-10QU100 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 10NS IND TEMP GRN RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-15AC100 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 5V ISP CPLD 100 PIN 15NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508AS-15AI100 | 功能描述:CPLD - 復雜可編程邏輯器件 128 MC CPLD 15NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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